ASAHI KASEI

[AK4385]

MS0246-E-01

2006/01

- 16 -

Mode Control Interface

Internal registers may be written by 3-wire µP interface pins, CSN, CCLK and CDTI. The data on this interface consists

of Chip Address (2bits, C1/0; fixed to “01”), Read/Write (1bit; fixed to “1”, Write only), Register Address (MSB first,

5bits) and Control Data (MSB first, 8bits). AK4385 latches the data on the rising edge of CCLK, so data should clocked

in on the falling edge. The writing of data becomes valid by CSN “

↑”. The clock speed of CCLK is 5MHz (max).

PDN = “L” resets the registers to their default values. The internal timing circuit is reset by RSTN bit, but the registers are

not initialized.

CDTI

CCLK

CSN

C1

0

12

3

4

5

6

7

8

9

10

11

12

13

14

15

D4

D5

D6

D7

A1

A2

A3

A4

R/W

C0

A0

D0

D1

D2

D3

C1-C0:

Chip Address (Fixed to “01”)

R/W:

READ/WRITE (Fixed to “1”, Write only)

A4-A0:

Register Address

D7-D0:

Control Data

Figure 8. Control I/F Timing

*AK4385 does not support the read command and chip address. C1/0 and R/W are fixed to “011”

*When the AK4385 is in the power down mode (PDN = “L”) or the MCLK is not provided, writing into the control

register is inhibited.

Register Map

Addr

Register Name

D7

D6

D5

D4

D3

D2

D1

D0

00H

Control 1

ACKS

0

0

DIF2

DIF1

DIF0

PW

RSTN

01H

Control 2

DZFE

DZFM

SLOW

DFS1

DFS0

DEM1

DEM0

SMUTE

02H

Control 3

0

0

0

0

0

DZFB

0

0

03H

Lch ATT

ATT7

ATT6

ATT5

ATT4

ATT3

ATT2

ATT1

ATT0

04H

Rch ATT

ATT7

ATT6

ATT5

ATT4

ATT3

ATT2

ATT1

ATT0

Notes:

For addresses from 05H to 1FH, data must not be written.

When PDN pin goes “L”, the registers are initialized to their default values.

When RSTN bit goes “0”, the only internal timing is reset and the registers are not initialized to their default

values.

All data can be written to the register even if PW or RSTN bit is “0”.