MSC8122 datasheet(21/88 Pages) FREESCALE

21 / 88 page

Direct Slave Interface, System Bus, Ethernet, and Interrupt Signals

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

1-11

Input/ Output Bus Request2

When an external arbiter is used, the MSC8122 asserts this pin as an output to request ownership of the

bus. When the MSC8122 controller is used as an internal arbiter, an external master asserts this pin as an

input to request bus ownership.

Input/ Output Bus Grant2

When the MSC8122 acts as an internal arbiter, it asserts this pin as an output to grant bus ownership to

an external bus master. When an external arbiter is used, it asserts this pin as an input to grant bus

ownership to the MSC8122.

DBG

Input/ Output Data Bus Grant2

When the MSC8122 acts as an internal arbiter, it asserts this pin as an output to grant data bus ownership

to an external bus master. When an external arbiter is used, it asserts this pin as an input to grant data

bus ownership to the MSC8122.

ABB

IRQ4

Input/ Output

Input

Address Bus Busy1

The MSC8122 asserts this pin as an output for the duration of the address bus tenure. Following an

AACK, which terminates the address bus tenure, the MSC8122 deasserts ABB for a fraction of a bus

cycle and then stops driving this pin. The MSC8122 does not assume bus ownership as long as it senses

this pin is asserted as an input by an external bus master.

Interrupt Request 4

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

DBB

IRQ5

Input/ Output

Input

Data Bus Busy1

The MSC8122 asserts this pin as an output for the duration of the data bus tenure. Following a TA, which

terminates the data bus tenure, the MSC8122 deasserts DBB for a fraction of a bus cycle and then stops

driving this pin. The MSC8122 does not assume data bus ownership as long as it senses that this pin is

asserted as an input by an external bus master.

Interrupt Request 5

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

Input/ Output

Bus Transfer Start

Assertion of this pin signals the beginning of a new address bus tenure. The MSC8122 asserts this signal

when one of its internal bus masters begins an address tenure. When the MSC8122 senses that this pin is

asserted by an external bus master, it responds to the address bus tenure as required (snoop if enabled,

access internal MSC8122 resources, memory controller support).

AACK

Input/ Output Address Acknowledge

A bus slave asserts this signal to indicate that it has identified the address tenure. Assertion of this signal

terminates the address tenure.

ARTRY

Input/ Output Address Retry

Assertion of this signal indicates that the bus master should retry the bus transaction. An external master

asserts this signal to enforce data coherency with its caches and to prevent deadlock situations.

D[0–31]

Input/ Output Data Bus Bits 0–31

In write transactions, the bus master drives the valid data on this bus. In read transactions, the slave

drives the valid data on this bus.

Reserved

DP0

DREQ1

EXT_BR2

Input

Input/ Output

Input

The primary configuration selection (default after reset) is reserved.

System Bus Data Parity 0

The agent that drives the data bus also drives the data parity signals. The value driven on the data parity

0 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 0 and

D[0–7].

DMA Request 1

Used by an external peripheral to request DMA service.

External Bus Request 2

An external master asserts this pin to request bus ownership from the internal arbiter.

Table 1-5.

DSI, System Bus, Ethernet, and Interrupt Signals (Continued)

Signal Name

Type

Description

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