STW81100 datasheet(7/29 Pages) STMICROELECTRONICS

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STW81100

Notes: 1. Frequency step higher than FOUT/4096 (i.e. N values less than 4096) can be used but it is not guaranteed the channel contiguity

(Only configurations with B>A and fPFD

≤ 10 MHz are allowed)

2. see relationship between ICP and REXT in the Circuit Description section (Charge Pump)

3. PFD frequency leakage (400KHz) and harmonics

4. Guaranteed by design and characterization.

Table 7. Phase Noise Performance1

Symbol

Parameter

Test Condition

Min

Typ

Max

Units

ILOBUF

Current Consumption

DIV4 Buff

DIV2 Buff

Direct Output

EXTERNAL VCO (Test purpose only)

fINVCO

Frequency range

3.3

4.4

GHz

Input level

dBm

VINDC

DC Input level

IEXTBUF

Current Consumption

VCO Internal Buffer

PLL MISCELLANEOUS

IPLL

Current Consumption

Input Buffer, Prescaler, Digital

Dividers, misc

tLOCK

Lock up time4

40 KHz PLL bandwidth; within

1 ppm of frequency error

150

µs

Parameter

Test Condition

Min

Typ

Max

Units

In Band Phase Noise – Closed Loop2

Normalized In Band Phase Noise

Floor

ICP= 2mA, PLL BW = 50KHz;

including reference clock contribution

-212

dBc/Hz

In Band Phase Noise Floor

Direct Output

-212+20log(N)+10log(fPFD)dBc/Hz

In Band Phase Noise Floor

Divider by 2

-218+20log(N)+10log(fPFD)dBc/Hz

In Band Phase Noise Floor

Divider by 4

-224+20log(N)+10log(fPFD)dBc/Hz

PLL Integrated Phase Noise with Divider by 2

Integrated Phase Noise (single

sided) 400Hz to 4MHz

ICP = 4mA, fPFD = 400KHz

(N = 10000), PLL BW = 15KHz

-39

-37

dBc

Integrated Phase Noise (single

sided) 100Hz to 25MHz

-38

-36

dBc

VCO A Direct (3300MHz-3900MHz) – Open Loop

Phase Noise @ 1 KHz

-56

-53

dBc/Hz

Phase Noise @ 10 KHz

-83

-82

dBc/Hz

Phase Noise @ 100 KHz

-105

-102

dBc/Hz

Phase Noise @ 1 MHz

-128

-125

dBc/Hz

Phase Noise @ 10 MHz

-148

-145

dBc/Hz

Phase Noise @ 40 MHz

-156

-153

dBc/Hz

Table 6. Electrical Characteristcs (continued)

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