PI7C8152AMA datasheet(84/90 Pages) PERICOM

84 / 90 page

PI7C8152A & PI7C8152B

2-PORT PCI-TO-PCI BRIDGE

ADVANCE INFORMATION

Page 84 of 90

October 16, 2003 – Revision 1.11

12.1.37

SECONDARY MASTER TIMEOUT COUNTER – OFFSET 80h

Bit

Function

Type

Description

31:16

Secondary

Timeout

R/W

Secondary timeout occurs after 215 PCI clocks.

Reset to 8000h.

12.1.38

CAPABILITY ID REGISTER – OFFSET DCh

Bit

Function

Type

Description

7:0

Enhanced

Capabilities ID

R/O

Read as 01h to indicate that these are power management enhanced

capability registers.

12.1.39

NEXT ITEM POINTER REGISTER – OFFSET DCh

Bit

Function

Type

Description

15:8

Next Item

Pointer

R/O

Read as 00h. No other ECP registers.

12.1.40

POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET

DCh

Bit

Function

Type

Description

18:16

Power

Management

Revision

R/O

Read as 010 to indicate the device is compliant to Revision 1.1 of

PCI Power Management Interface Specifications.

PME_L Clock

R/O

Read as 0 to indicate PI7C8152x does not support the PME_L pin.

Auxiliary Power

R/O

Read as 0 to indicate PI7C8152x does not support the PME_L pin or

an auxiliary power source.

Device Specific

Initialization

R/O

Read as 0 to indicate PI7C8152x does not have device specific

initialization requirements.

24:22

Reserved

R/O

Read as 0

D1 Power State

Support

R/O

Read as 1 to indicate PI7C8152x supports the D1 power management

state.

D2 Power State

Support

R/O

Read as 1 to indicate PI7C8152x supports the D2 power management

state.

31:27

PME_L Support

R/O

Read as 0 to indicate PI7C8152x does not support the PME_L pin.

12.1.41

POWER MANAGEMENT DATA REGISTER – OFFSET E0h

Bit

Function

Type

Description

1:0

Power State

R/W

Indicates the current power state of PI7C8152x. If an unimplemented

power state is written to this register, PI7C8152x completes the write

transaction, ignores the write data, and does not change the value of

the field. Writing a value of D0 when the previous state was D3

cause a chip reset without asserting S_RESET_L

00: D0 state

01: D1 state

10: D2 state

11: D3 state

Reset to 0

7:2

Reserved

R/O

Read as 0

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