HTG2190 datasheet(9/50 Pages) HOLTEK

9 / 50 page

HTG2190

Rev. 1.20

July 5, 2002

T 1

T 2

T 3

T 4

T 1

T 2

T 3

T 4

T 1

T 2

T 3

T 4

. e t c h I N S T ( P C )

E x e c u t e I N S T ( P C - 1 )

. e t c h I N S T ( P C + 1 )

E x e c u t e I N S T ( P C )

. e t c h I N S T ( P C + 2 )

E x e c u t e I N S T ( P C + 1 )

P C

P C + 1

P C + 2

S y s t e m C l o c k

O S C 2 ( R C o n l y )

P C

B a n k 0

B a n k 1

B a n k 2

B a n k 7

8 1 9 2 ´ 1 6

B i t s

0 0 0 0 H

1 . . . H

S t a c k

B a n k P o i n t e r

R e g i s t e r

B i t 7 , B i t 6 , B i t 5

A 1 5 , A 1 4 , A 1 3

B u f f e r

L a t c h d a t a o n E x e c u t i o n o f J u m p o r C a l l I n s t r u c t i o n

6 4 K P r o g r a m R O M A d d r e s s i n g A r c h i t e c t u r e

1 3 b i t s

P r o g r a m

C o u n t e r

2 0 0 0 H

3 . . . H

4 0 0 0 H

5 . . . H

E 0 0 0 H

. . . . H

Execution flow

Functional Description

Execution flow

The system clock for the HTG2190 is derived from ei-

ther a crystal or an RC oscillator. It is internally divided

into four non-overlapping clocks. One instruction cycle

consists of four system clock cycles.

Instruction fetching and execution are pipelined in such

a way that a fetch takes one instruction cycle while de-

coding and execution takes the next instruction cycle.

However, the pipelining scheme causes each instruc-

tion to effectively execute within one cycle. If an instruc-

tion changes the program counter, two cycles are

required to complete the instruction.

Program counter

- PC

The 13-bit program counter (PC) controls the sequence

in which the instructions stored in program ROM are ex-

ecuted.

After accessing a program memory word to fetch an in-

struction code, the contents of the program counter are

incremented by one. The program counter then points to

the memory word containing the next instruction code.

When executing a jump instruction, conditional skip ex-

ecution, loading PCL register, subroutine call, initial re-

set, internal interrupt, external interrupt or return from

subroutine, the PC manipulates the program transfer by

loading the address corresponding to each instruction.

The conditional skip is activated by instruction. Once the

condition is met, the next instruction, fetched during the

current instruction execution, is discarded and a dummy

cycle takes its place while the correct instruction is ob-

tained.

The lower byte of the program counter (PCL) is a

read/write register (06H). Moving data into the PCL per-

Mode

Program ROM Address

*15

*14 *13

*12

*11

*10

Initial reset

External or serial

input interrupt

Timer/Event

Counter 0 overflow

Timer/Event

Counter 1 overflow

Timer 2 overflow

Timer 3 overflow

Skip

PC+2

Loading PCL

*15

*14 *13

*12

*11

*10

@1 @0

Jump, call branch

BP.7 BP.6 BP.5 #12

#11 #10

Return from

subroutine

S15 S14 S13 S12 S11 S10

Program ROM address

Note: *15~*0: Program ROM address

S15~S0: Stack register bits

@7~@0: PCL bits

BP.5~BP.7: Bit 5~7 of bank pointer (04H)

#12~#0: Instruction code bits

HTG2190 bảng dữ liệu(PDF) 9 Page - Holtek Semiconductor Inc

HTG2190 bảng dữ liệu(HTML) 9 Page - Holtek Semiconductor Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

bảng dữ liệu tải về

Link URL