SC2596SETRT datasheet(10/13 Pages) SEMTECH

10 / 13 page

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SC2596

PRELIMINARY

POWER MANAGEMENT

Application Information (Cont.)

Application_2: Lower Power Loss Configuration for

SSTL-2

If power loss is a major concern, separating the PVCC

form AVCC and VDDQ will be a good choice (Figure 2).

The PVCC can operate at lower voltage (1.8V to 2.5V) if

2.5V voltage is applied on AVCC and the VDDQ, the source

current is lower due to the lower operating voltage ap-

plied on the PVCC.

Figure 2: Lower power loss for SSTL-2(DDR-I).

Application_3: High Source Current Configuration

If there is a need for VTT to source more current, espe-

cially for DDR-II applications, the system designer can tie

the AVCC and PVCC to 3.3V while has the VDDQ tie to 1.

8V. This configuration can ensure more than 2A source

and sink capability from the VTT rail.

Figure 4: High current set up for SSTL-18(DDR-II).

Notes:

(a) The preferred configuration for DDR-I applications

is to tie AVCC and PVCC to VDDQ, which is typically 2.5V.

(b) If AVCC and PVCC rails are tied together, then the

VDDQ cannot lead the AVCC and PVCC.

Figure 3: Lower power loss for SSTL-18(DDR-II).

10nF

VDDQ

0.9V

Cout

220uF

Cin1

1uF

SC2596

GND

VSENSE

VREF

VDDQ

AVCC

PVCC

VTT

Cin2

100uF

Cref

100nF

1.8V

VREF

2.5V

10nF

0.9V

VDDQ

0.9V

Cout

220uF

Cin1

1uF

SC2596

GND

VSENSE

VREF

VDDQ

AVCC

PVCC

VTT

Cin2

100uF

Cref

100nF

VREF

1.8V

3.3V

VREF

Cout

220uF

10nF

2.5V

1.25V

VTT

Cin1

100uF

Cref

100nF

Cin2

1uF

SC2596

GND

VSENSE

VREF

VDDQ

AVCC

PVCC

VTT

1.25V

VDDQ

2.5V

PVCC

2.5V

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