HT82M9BEE datasheet(13/47 Pages) HOLTEK

13 / 47 page

HT82M9BEE/HT82M9BAE

Rev. 1.20

August 13, 2007

TO PDF

RESET Conditions

RES reset during power-up

RES reset during normal operation

RES wake-up HALT

WDT time-out during normal operation

WDT wake-up HALT

Note:

²u² stands for ²unchanged²

To guarantee that the system oscillator is started and

stabilized, the SST (System Start-up Timer) provides an

extra delay of 1024 system clock pulses when the sys-

tem resets (power-up, WDT time-out or RES reset) or

the system awakes from the HALT state.

When a system reset occurs, the SST delay is added

during the reset period. Any wake-up from HALT will en-

able the SST delay.

The functional unit chip reset status are shown below.

Program Counter

000H

Interrupt

Disable

Prescaler

Clear

WDT

Clear. After master reset,

WDT begins counting

Timer/event Counter

Off

Input/output Ports

Input mode

Stack Pointer

Points to the top of the stack

V D D

R E S

Reset Circuit

W a r m R e s e t

W D T

H A L T

C o l d

R e s e t

R E S

S y s t e m R e s e t

S S T

1 0 - b i t R i p p l e

C o u n t e r

O S C 1

Reset Configuration

t S S T

R E S

V D D

S S T T i m e - o u t

C h i p R e s e t

Reset Timing Chart

The registers status are summarized in the following table.

Reset

(Power On)

WDT

Time-out

(Normal

Operation)

RES Reset

(Normal

Operation)

RES Reset

(HALT)

WDT

Time-out

(HALT)*

USB Reset

(Normal)

USB Reset

(HALT)

Program

Counter

000H

MP0

xxxx xxxx

uuuu uuuu

MP1

xxxx xxxx

uuuu uuuu

0000 0000

ACC

xxxx xxxx

uuuu uuuu

TBLP

xxxx xxxx

uuuu uuuu

TBLH

xxxx xxxx

uuuu uuuu

WDTS

1000 0111

uuuu uuuu

1000 0111

STATUS

--00 xxxx

--1u uuuu

--00 uuuu

--11 uuuu

--uu uuuu

--01 uuuu

INTC

-000 0000

-uuu uuuu

-000 0000

TMR0

xxxx xxxx

0000 0000

uuuu uuuu

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