SC453TSTRT datasheet(20/23 Pages) SEMTECH

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POWER MANAGEMENT

SC453

Based on the above calculations, we choose N = 4 for the

input capacitor.

Step 9: OVP

No calculations are necessary for Over-Voltage Protection.

If V

CORE is greater than +14% of the DAC (i.e., out of the

power good window), the SC453 will latch off and hold the

low-side driver on permanently (for each phase). Either

the power or EN must be recycled to clear the latch. The

latch is disabled during soft-start and VID/DeeperSleep

transitions. The latch is enabled if V

CORE exceeds 2V even

during VID/DeeperSleep transitions to ensure that the

processor maximum is not exceeded. The table on Page

13 is a summary of fault conditions using SC453.

Step 10: Soft-Start/DAC Slew Control

The soft-start cap C21 in the SC453 design serves three

conditions: 1) to deﬁne the soft-start ramp; 2) to deﬁne

the DAC slew rate during sleep and VID transitions (dur-

ing VID transitions the SS current is nominally +/- 120μA.

During sleep transitions the SS current increases to +/-

240μA); 3) during start-up, the SS current is normally +/-

6.5μA.

We will be doing three soft-start exercises based on the

above three conditions for SC453 application:

Step 8: Calculate Input RMS Current

In order to calculate the worst-case input RMS current, we

need to assume the efﬁciency at V

IN_MIN and full load. From

the measurement result, we are safe to assume 80%,

(this number is very conservative, actual efﬁciency should

be much higher). The actual converter efﬁciency depends

on component selection, layout, airﬂow, etc.

POUT IMAX_FL VMAX_FL

⋅

POUT 23.64 W

POUT

85%

IIN_DC

VINMIN

VMAX_FL

VINMIN

IIN_DC 3.476 A

IRMS

IMAX_FL

() IIN_DC

−

⎡⎣

⎤

⋅

IIN_DC

−

()

⋅

⎡

⎣

⎤

IRMS 7.116 A

CI_RMS 2A

10μF@25V, MLCC cap from Panasonic is rated 2A RMS.

CI_NUM ceil

IRMS

CI_RMS

⎛

⎜

⎝

⎞

⎠

CI_NUM 4

The calculation indicates four of these MLCC caps satisfy

the worst-case RMS current requirement.

Input Capacitance Calculation:

(based on ripple voltage)

dVin is the allowable input ripple voltage contributed by

the amount of input capacitance. For this exercise, we

use 250mV as the allowable input ripple voltage. The

maximum value occurs at D = 0.5

Applications Information (Cont.)

dVin

250mV

DMAX 0.5

Tin

CIN_MIN

IPEAK

DMAX DMAX

−

⎛

⎝

⎞

⋅

Tin

dVin

⋅

CIN_MIN 3.341 10

−

CIN 10μF

NIN_MIN_RIPPLE

ceil

CIN_MIN

CIN

⎛

⎜

⎝

⎞

⎠

NIN_MIN_RIPPLE 4

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