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SC2618 bảng dữ liệu(PDF) 7 Page - Semtech Corporation |
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SC2618 bảng dữ liệu(HTML) 7 Page - Semtech Corporation |
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7 / 9 page ![]() 7 2004 Semtech Corp. www.semtech.com POWER MANAGEMENT SC2618 Layout Guidelines Careful attention to layout requirements are necessary for successful implementation of the SC2618 controller. High currents switching at up to 500kHz are present in the application and their effect on ground plane voltage differentials must be understood and minimized. 1). The high power parts of the circuit should be laid out first. A ground plane should be used, the number and position of ground plane interruptions should be such as to not unnecessarily compromise ground plane integrity. Isolated or semi-isolated areas of the ground plane may be deliberately introduced to constrain ground currents to particular areas, for example the input capacitor and bottom FET ground. 2). The loop formed by the Input Capacitor(s) (Cin), the Top FET (Q1) and the Bottom FET (Q2) must be kept as small as possible. This loop contains all the high current, fast transition switching. Connections should be as wide and as short as possible to minimize loop inductance. Minimizing this loop area will a) reduce EMI, b) lower ground injection currents, resulting in electrically “cleaner” grounds for the rest of the system and c) minimize source ringing, resulting in more reliable gate switching signals. Cin should consist of the bulk input capacitors and must be supplemented with one or more ceramic decoupling capacitors as close as possible to the FETs 3). The connection between the junction of Q1, Q2 and the output inductor should be a wide trace or copper region. It should be as short as practical. Since this con- nection has fast voltage transitions, keeping this con- nection short will minimize EMI. The connection between the output inductor and the output capacitors should be a wide trace or copper area, there are no fast voltage or current transitions in this connection and length is not so important, however adding unnecessary impedance will reduce efficiency. L Cout 10uF U1 SC2618 5 6 4 1 3 2 VCC DH BST FB DL GND Q1 10 VPWR IN Vout GND 0.1uF Cin Q2 VBST IN VCC IN |
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