6.6 I2C Interface Timing

Minimum and maximum specifications are over –40°C to 125°C and V+ = 1.4V to 5.5V (unless otherwise noted)(1)

FAST MODE

FAST MODE PLUS

HIGH-SPEED MODE

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

f(SCL)

SCL operating frequency

0.001

0.4

0.001

1

0.001

3.4

MHz

t(BUF)

Bus-free time between STOP

and START conditions

600

–

500

160

–

ns

t(HDSTA)

Hold time after repeated START

condition.

After this period, the first clock is

generated.

100

–

100

100

–

ns

t(SUSTA)

Repeated START condition

setup time

100

–

100

100

–

ns

t(SUSTO)

STOP condition setup time

600

–

260

160

–

ns

t(HDDAT)

Data hold time(2)

10

900

10

150

10

105

ns

t(SUDAT)

Data setup time

100

–

10

10

–

ns

t(LOW)

SCL clock low period

1300

–

500

160

–

ns

t(HIGH)

SCL clock high period

600

–

260

60

–

ns

t(VDAT)

Data valid time (data response

time)(3)

900

450

ns

tF

SDA, SCL fall time

–

300

120

–

80

ns

tR

SDA, SCL rise time

–

300

–

120

–

80

ns

ttimeout

Timeout (SCL = Low or SDA =

Low)

30

30

–

40

ms

tLPF

Glitch suppression filter

50

50

–

40

ns

(1)

The controller and device have the same V+ value. Values are based on statistical analysis of samples tested during initial release

(2)

The maximum t(HDDAT) can be 0.9 µs for fast mode, and is less than the maximum t(VDAT) by a transition time.

(3)

t(VDAT) = time for data signal from SCL LOW to SDA output (HIGH to LOW, depending on which is worse).

SCL

SDA

t

(LOW)

t

R

t

F

t

(HDSTA)

t

(HDSTA)

t

(HDDAT)

t

(BUF)

t

(SUDAT)

t

(HIGH)

t

(SUSTA)

t

(SUSTO)

P

S

S

P

Figure 6-1. I2C Timing Diagram

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TMP113

SBOSAJ5 – DECEMBER 2024

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