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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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HT46R46E bảng dữ liệu(PDF) 7 Page - Holtek Semiconductor Inc |
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HT46R46E bảng dữ liệu(HTML) 7 Page - Holtek Semiconductor Inc |
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7 / 73 page  Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD Conditions tRES External Reset Low Pulse Width ¾¾ 1 ¾¾ ms tSST System Start-up Timer Period ¾ Wake-up from HALT ¾ 1024 ¾ *tSYS tLVR Low Voltage Reset Time ¾¾ 0.25 1 2 ms tINT Interrupt Pulse Width ¾¾ 1 ¾¾ ms tAD1 A/D Clock Period - HT46R46E ¾¾ 0.5 ¾¾ ms tAD2 A/D Clock Period - HT46R47E/HT46R48AE/HT46R49E ¾¾ 1 ¾¾ ms tADC1 A/D Conversion Time - HT46R46E ¾¾ ¾ 64 ¾ tAD1 tADC2 A/D Conversion Time - HT46R47E/HT46R48AE/HT46R49E ¾¾ ¾ 76 ¾ tAD2 tADCS1 A/D Sampling Time - HT46R46E ¾¾ ¾ 32 ¾ tAD1 tADCS2 A/D Sampling Time - HT46R47E/HT46R48AE/HT46R49E ¾¾ ¾ 32 ¾ tAD2 Note: *tSYS=1/fSYS EEPROM - A.C. Characteristics Ta=25 °C Symbol Parameter Remark Standard Mode* VCC=5V ±10% Unit Min. Max. Min. Max. fSK Clock Frequency ¾¾ 100 ¾ 400 kHz tHIGH Clock High Time ¾ 4000 ¾ 600 ¾ ns tLOW Clock Low Time ¾ 4700 ¾ 1200 ¾ ns tr SDA and SCL Rise Time Note ¾ 1000 ¾ 300 ns tf SDA and SCL Fall Time Note ¾ 300 ¾ 300 ns tHD:STA START Condition Hold Time After this period the first clock pulse is generated 4000 ¾ 600 ¾ ns tSU:STA START Condition Setup Time Only relevant for repeated START condition 4000 ¾ 600 ¾ ns tHD:DAT Data Input Hold Time ¾ 0 ¾ 0 ¾ ns tSU:DAT Data Input Setup Time ¾ 200 ¾ 100 ¾ ns tSU:STO STOP Condition Setup Time ¾ 4000 ¾ 600 ¾ ns tAA Output Valid from Clock ¾¾ 3500 ¾ 900 ns tBUF Bus Free Time Time in which the bus must be free before a new transmission can start 4700 ¾ 1200 ¾ ns tSP Input Filter Time Constant (SDA and SCL Pins) Noise suppression time ¾ 100 ¾ 50 ns tWR Write Cycle Time ¾¾ 5 ¾ 5ms Note: These parameters are periodically sampled but not 100% tested * The standard mode means VCC=2.2V to 5.5V HT46R46E/C46E/R47E/C47E/R48AE/C48AE/R49E Rev. 1.20 7 August 15, 2007 |
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