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SC486

POWER MANAGEMENT

Layout Guidelines (Cont.)

Next, looking at the switcher power section, the schematic in Figure 10 below shows the power section for VDDQ:

+

C14

220u/15m

+

C13

220u/15m

VDDQ

C5

2n2/50V

VBAT

L1

1u5

C6

0u1/25V

C7

10u/25V

C8

10u/25V

S

1

S

2

S

3

G

4

D

5

D

6

D

7

D

8

Q1 IRF7811AV

S

1

S

2

S

3

G

4

D

5

D

6

D

7

D

8

Q2

FDS6676S

Figure 10: VDDQ Power Section and Input Loop

The highest di/dts occur in the input loop (highlighted in red) and thus this should be kept as small as possible. The

input capacitors should be placed with the highest frequency capacitors closest to the loop to reduce EMI. Use large

copper pours to minimize losses and parasitics. See Figure 11 below for an example.

Figure 11: Example VDDQ Power Section Layout