M58PR256LE datasheet(16/119 Pages) STMICROELECTRONICS

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Signal descriptions

M58PR256LE, M58PR512LE, M58PR001LE

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2.7

Reset (RP)

The Reset input provides a hardware reset of the memory. When Reset is at VIL, the

memory is in reset mode, this means the outputs are high impedance and the current

consumption is reduced to the reset supply current IDD2. Refer to Table 27: DC

characteristics - currents for the value of IDD2. After Reset, all blocks are in the locked state

and the Configuration Register is reset. When Reset is at VIH, the device is in normal

operation. Exiting reset mode the device enters asynchronous read mode, but a negative

transition of Chip Enable or Latch Enable is required to ensure valid data outputs.

The Reset pin can be interfaced with 3 V logic without any additional circuitry, and can be

tied to VRPH (refer to Table 28: DC characteristics - voltages).

2.8

Deep power-down (DPD)

The deep power-down input is used to put the device in deep power-down mode.

When the device is in Standby mode and the Enhanced Configuration Register bit ECR15 is

set, asserting the deep power-down input will cause the memory to enter the deep power-

down mode.

When the device is in the deep power-down mode, the memory cannot be modified and the

data is protected.

The polarity of the DPD pin is determined by ECR14. The deep power-down input is active

Low by default.

2.9

Latch Enable (L)

Latch Enable latches the address bits on its rising edge. The address latch is transparent

when Latch Enable is at VIL and it is inhibited when Latch Enable is at VIH. Latch Enable can

be kept Low (also at board level) when the Latch Enable function is not required or

supported.

2.10

Clock (K)

The clock input synchronizes the memory to the microcontroller during synchronous read

operations; the address is latched on a Clock edge when Latch Enable is at VIL. Clock is

ignored during asynchronous read and in write operations.

2.11

Wait (WAIT)

Wait is an output signal used during synchronous read to indicate whether the data on the

output bus are valid. This output is high impedance when Chip Enable is at VIH, Output

Enable is at VIH, or Reset is at VIL. It can be configured to be active during the wait cycle or

one data cycle in advance.

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