HT46R01 datasheet(33/60 Pages) HOLTEK

33 / 60 page

HT46R01/HT46R02/HT46R03

Rev. 1.00

September 21, 2007

Interrupts

Interrupts are an important part of any microcontroller

system. When an external event or an internal function

such as a Timer/Event Counter or an A/D converter re-

quires microcontroller attention, their corresponding in-

terrupt will enforce a temporary suspension of the main

program allowing the microcontroller to direct attention

to their respective needs. Each device contains a single

external interrupt and several internal interrupts func-

tions. The external interrupt is controlled by the action of

the external INT pin, while the internal interrupts are

controlled by the Timer/Event Counter overflows and

the A/D converter interrupt.

Interrupt Register

Overall interrupt control, which means interrupt enabling

and request flag setting, is controlled by a single INTC0

located in the Data Memory. By controlling the appropri-

ate enable bits in these registers each individual inter-

rupt can be enabled or disabled. Also when an interrupt

occurs, the corresponding request flag will be set by the

microcontroller. The global enable flag if cleared to zero

will disable all interrupts.

I N T C 0 R e g i s t e r

H T 4 6 R 0 1

M a s t e r I n t e r r u p t G l o b a l E n a b l e

1 : g l o b a l e n a b l e

0 : g l o b a l d i s a b l e

F o r t e s t m o d e u s e o n l y .

M u s t b e w r i t t e n a s " 0 " o t h e r w i s e m a y

r e s u l t i n u n p r e d i c t a b l e o p e r a t i o n

b 7

b 0

E T 0 I E E I

E M I

T i m e r / E v e n t C o u n t e r I n t e r r u p t E n a b l e

1 : e n a b l e

0 : d i s a b l e

T i m e r / E v e n t C o u n t e r I n t e r r u p t R e q u e s t F l a g

1 : a c t i v e

0 : i n a c t i v e

E I F

T 0 F

E A D I

A D F

A / D C o n v e r t e r I n t e r r u p t E n a b l e

1 : e n a b l e

0 : d i s a b l e

E x t e r n a l I n t e r r u p t E n a b l e

1 : e n a b l e

0 : d i s a b l e

E x t e r n a l I n t e r r u p t R e q u e s t F l a g

1 : a c t i v e

0 : i n a c t i v e

A / D C o n v e r t e r R e q u e s t F l a g

1 : a c t i v e

0 : i n a c t i v e

INTC0 Register

- HT46R01

I N T C 0 R e g i s t e r

H T 4 6 R 0 2 / H T 4 6 R 0 3

M a s t e r I n t e r r u p t G l o b a l E n a b l e

1 : g l o b a l e n a b l e

0 : g l o b a l d i s a b l e

F o r t e s t m o d e u s e o n l y .

M u s t b e w r i t t e n a s " 0 " o t h e r w i s e m a y

r e s u l t i n u n p r e d i c t a b l e o p e r a t i o n

b 7

b 0

E T 0 I E E I

E M I

T i m e r / E v e n t C o u n t e r 0 I n t e r r u p t E n a b l e

1 : e n a b l e

0 : d i s a b l e

T i m e r / E v e n t C o u n t e r 0 I n t e r r u p t R e q u e s t F l a g

1 : a c t i v e

0 : i n a c t i v e

E I F

T 0 F

E x t e r n a l I n t e r r u p t E n a b l e

1 : e n a b l e

0 : d i s a b l e

E x t e r n a l I n t e r r u p t R e q u e s t F l a g

1 : a c t i v e

0 : i n a c t i v e

T 1 F

E T 1 I

T i m e r / E v e n t C o u n t e r 1 I n t e r r u p t E n a b l e

1 : e n a b l e

0 : d i s a b l e

T i m e r / E v e n t C o u n t e r 1 I n t e r r u p t R e q u e s t F l a g

1 : a c t i v e

0 : i n a c t i v e

INTC0 Register

- HT46R02/HT46R03

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