HT45RM03 datasheet(16/54 Pages) HOLTEK

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HT45RM03

Rev. 1.10

February 16, 2007

matter what the operation mode is, writing a

²0² to ET0I

or ET1I disables the related interrupt service. When the

PFD function is selected, executing

²SET [PD].0² instruc-

tion to enable the PFD output and executing

²CLR

[PD].0

² instruction to disable the PFD output.

After this procedure, the timer/event function can be op-

erated normally. The bit0~bit2 of the TMR0C/TMR1C

can be used to define the pre-scaling stages of the inter-

nal clock sources of timer/event counter. The definitions

are as shown. The overflow signal of timer/event coun-

ter can be used to generate the PFD signal.

In the case of timer/event counter off condition, writing

data to the timer/event counter preload register also re-

loads that data to the timer/event counter. But if the

timer/event counter is turn-on, data written to the

timer/event counter is kept only in the timer/event coun-

ter preload register. The timer/event counter still contin-

ues its operation until an overflow occurs. When the

timer/event counter (reading TMR0/TMR1) is read, the

clock is blocked to avoid errors, as this may results in a

counting error. Blocking of the clock should be taken

into account by the programmer. It is strongly recom-

mended to load a desired value into the TMR0/TMR1

counter, for proper operation since the initial value of

TMR0/TMR1 is unknown. Due to the timer/event

scheme, the programmer should pay special attention

on the instruction to enable then disable the timer for the

first time, whenever there is a need to use the

timer/event function, to avoid unpredictable result.

Bit No.

Label

Function

0~2

T0PSC0~

T0PSC2

To define the prescaler stages, T0PSC2, T0PSC1, T0PSC0=

000: fINT=fSYS

001: fINT=fSYS/2

010: fINT=fSYS/4

011: fINT=fSYS/8

100: fINT=fSYS/16

101: fINT=fSYS/32

110: fINT=fSYS/64

111: fINT=fSYS/128

T0E

To define the TMR0 active edge of Timer/Event Counter 0

(0=active on low to high; 1=active on high to low)

T0ON

To enable or disable Timer 0 counting (0=disabled; 1=enabled)

Unused bit, read as

²0²

T0M0

T0M1

To define the operating mode, T0M1, T0M0=

01=Event count mode (external clock)

10=Timer mode (internal clock)

11=Pulse width measurement mode

00=Unused

TMR0C (0EH) Register

Bit No.

Label

Function

0~2

T1PSC0~

T1PSC2

To define the prescaler stages, T1PSC2, T1PSC1, T1PSC0=

000: fINT=fSYS

001: fINT=fSYS/2

010: fINT=fSYS/4

011: fINT=fSYS/8

100: fINT=fSYS/16

101: fINT=fSYS/32

110: fINT=fSYS/64

111: fINT=fSYS/128

T1E

To define the TMR1 active edge of Timer/Event Counter 1

(0=active on low to high; 1=active on high to low)

T1ON

To enable or disable Timer 1 counting (0=disabled; 1=enabled)

Unused bit, read as

²0²

T1M0

T1M1

To define the operating mode, T1M1, T1M0=

01=Event count mode (external clock)

10=Timer mode (internal clock)

11=Pulse width measurement mode

00=Unused

TMR1C (11H) Register

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