PPC440SPE-RNB667C datasheet(61/80 Pages) AMCC

61 / 80 page

PowerPC 440SPe Embedded Processor

Revision 1.23 - Sept 21, 2006

AMCC Proprietary

Preliminary Data Sheet

Input Max Allowable Overshoot (3.3V LVTTL)

VIMAO

+3.9

Input Max Allowable Undershoot (3.3V LVTTL)

VIMAU

-0.6

Output Max Allowable Overshoot (3.3V LVTTL)

VOMAO

+3.9

Output Max Allowable Undershoot (3.3V LVTTL)

VOMAU3

-0.6

Case Temperature

0+95

°C6

Notes:

1. PCI-X drivers meet PCI-X specifications.

2. SVREF = SVDD/2

3. The analog voltages used for the on-chip PLLs can be derived from the logic voltage, but must be filtered before entering the

PPC440SPe. See “Absolute Maximum Ratings” on page 58.

4. During chip power-up, OVDD should begin to ramp before VDD. External voltage should not be applied to the chip I/O pins before

OVDD is applied to the chip. A power-down cycle should complete (OVDD and VDD should both be below 0.4V) before a new power

up cycle is started.

5. LPDL is least positive down level; MPUL is most positive up level.

6. Case temperature, TC, is measured at top center of case surface with device soldered to circuit board.

Table 10. Input Capacitance

Parameter

Symbol

Maximum

Unit

Notes

Group 1 (2.5V SSTL I/O)

CIN1

5.7

Group 2 (3.3V LVTTL I/O)

CIN2

6.8

Group 3 (PCI-X I/O)

CIN3

5.1

Group 4 (Receivers)

CIN4

6.7

Group 5 (3.3V tolerant CMOS I/O)

CIN5

2.6

Table 9. Recommended DC Operating Conditions (Sheet 3 of 3)

Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended

conditions can affect device reliability.

Parameter

Symbol

Minimum

Typical

Maximum

Unit

Notes

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