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405EZ bảng dữ liệu(PDF) 49 Page - Applied Micro Circuits Corporation

tên linh kiện 405EZ
Giải thích chi tiết về linh kiện  PowerPC 405EZ Embedded Processor
PDF  54 Pages
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nhà sản xuất  AMCC [Applied Micro Circuits Corporation]
Trang chủ  http://www.amcc.com
Logo AMCC - Applied Micro Circuits Corporation

405EZ bảng dữ liệu(HTML) 49 Page - Applied Micro Circuits Corporation

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PPC405EZ – PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
AMCC Proprietary
49
Preliminary Data Sheet
ADC_InTrig
na
na
na
na
ADC_VRef
na
na
na
na
DAC_CRef
na
na
na
na
DAC_IOutP
nananana
DAC_IPTrig
19.1
8.7
DAC_IRRef
nananana
DAC_VRef
na
na
na
na
DAC_GRef
na
na
na
na
PWM_DivClk
19.1
8.7
5
PWM_OE[0]
19.1
8.7
5
PWM_OE[1:3]
19.1
8.7
5
PWM_TBA
19.1
8.7
5
PWM_1:15
19.1
8.7
5
IEEE_1588TS
19.1
8.7
Interrupts Interface
[IRQ0:4]
19.1
8.7
JTAG Interface
TCK
na
na
nananana
TDI
22.5
0
nananana
TCK
TDO
na
na
25
0
19.1
8.7
TCK
TMS
22.5
0
na
na
na
na
TCK
TRST
na
na
na
na
na
na
TCK
System Interface
GPIO000:31
na
na
na
na
19.1
8.7
GPIO100:20
na
na
na
na
19.1
8.7
Halt
22.5
0
nananana
TCK
SysErr
na
na
15
25.5
19.1
8.7
TCK
SysReset
na
na
na
na
19.1
8.7
async
TestEn
na
na
na
na
na
na
async
DebugEn
na
na
na
na
na
na
SysClk
na
na
na
na
na
na
Table 15. I/O Specifications—All CPU Speeds (Sheet 2 of 2)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. Timing shown is with EMAC noise filter
selected.
2. For all interfaces, I/O H is specified at 2.4 V and I/O L is specified at 0.4 V.
3. Maximum skew between IIC output signals is 6ns.
4. Maximum skew between all SPI output signals is 3ns. All SPI inputs signals are latched with less than 4ns of skew between
channels.
5. Maximum skew between all PWM output signals is 3.75ns. All PWM input signals are latched with less than 2.5ns of skew
between channels.
Signal
Input (ns)
Output (ns)
Output Current (mA)
Clock
Notes
Setup Time
(TIS min)
Hold Time
(TIH min)
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(min)
I/O L
(min)



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