CAT24WC03GLATE13 datasheet(7/14 Pages) CATALYST

7 / 14 page

Discontinued

Parts

CAT24WC03/05

Doc. No. 1005, Rev. F

Characteristics subject to change without notice

WRITE PROTECTION

The Write Protection feature allows the user to protect

against inadvertent programming of the memory array.

If the WP pin is tied to VCC, the upper half (locations 80H

to FFH for CAT24WC03 and locations 100H to 1FFH for

CAT24WC05) of the memory array is protected and

becomes read only. The CAT24WC03/05 will accept

both slave and byte addresses, but the memory location

accessed is protected from programming by the device’s

failure to send an acknowledge after the first byte of data

is received.

READ OPERATIONS

The READ operation for the CAT24WC03/05 is initiated

in the same manner as the write operation with the one

exception that the R/

W bit is set to a one. Three different

READ operations are possible: Immediate Address

READ, Selective READ and Sequential READ.

Immediate Address Read

The CAT24WC03/05 address counter contains the

address of the last byte accessed incremented by one.

In other words, if the last READ or WRITE access was

to address N, the READ immediately following would

access data from address N+1. If N=E (where E = 255

for the CAT24WC03 and 511 for the CAT24WC05), then

the counter will ‘wrap around’ to address 0 and continue

to clock out data. After the CAT24WC03/05 receives its

slave address information (with the R/

W bit set to one),

it issues an acknowledge, then transmits the 8-bit byte

requested. The master device does not send an

acknowledge but will generate a STOP condition.

Selective Read

Selective READ operations allow the Master device to

select at random any memory location for a READ

operation. The Master device first performs a ‘dummy’

write operation by sending the START condition, slave

address and byte address of the location it wishes to

read. After the CAT24WC03/05 acknowledge the word

address, the Master device resends the START condition

and the slave address, this time with the R/

W bit set to

one. The CAT24WC03/05 then responds with its

acknowledge and sends the 8-bit byte requested. The

master device does not send an acknowledge but will

generate a STOP condition.

Figure 8. Immediate Address Read Timing

SCL

SDA

8TH BIT

STOP

NO ACK

DATA OUT

SLAVE

ADDRESS

DATA

BUS ACTIVITY:

MASTER

SDA LINE

Figure 9. Selective Read Timing

SLAVE

ADDRESS

BUS ACTIVITY:

MASTER

SDA LINE

BYTE

ADDRESS (n)

DATA n

SLAVE

ADDRESS

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