PPC405CR – PowerPC 405CR Embedded Processor

38

AMCC

Revision 1.02 – January 11, 2005

Data Sheet

Table 15. I/O Specifications—266MHz

Notes:

1. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the

command is used by SDRAM.

2. SDRAM I/O timings are specified relative to a MemClkOut terminated into a lumped 10pF load.

3. SDRAM interface hold times are guaranteed at the PPC405CR package pin. System designers must use the PPC405CR

IBIS model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections,

and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring.

4. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.

5. I/O H is specified at 2.4 V and I/O L is specified at 0.4 V.

Signal

Input (ns)

Output (ns)

Output Current (mA)

Clock

Notes

Setup Time

Hold Time

Valid Delay

Hold Time

I/O H

(min)

I/O L

(min)

SDRAM Interface

BA1:0

n/a

n/a

5.5

1

19

12

MemClkOut

1, 2

BankSel0:3

n/a

n/a

4.5

1

19

12

MemClkOut

2

CAS

n/a

n/a

5.5

1

19

12

MemClkOut

1, 2

ClkEn0:1

n/a

n/a

3.9

1

40

25

MemClkOut

2

DQM0:3

n/a

n/a

4.9

1

19

12

MemClkOut

2

DQMCB

n/a

n/a

4.7

1

19

12

MemClkOut

2

ECC0:7

1.5

1

4.7

1

19

12

MemClkOut

2

MemAddr12:0

n/a

n/a

5.9

1

19

12

MemClkOut

1, 2

MemData0:31

1.5

1

4.8

1

19

12

MemClkOut

2

RAS

n/a

n/a

5.6

1

19

12

MemClkOut

1, 2

WE

n/a

n/a

5.6

1

19

12

MemClkOut

1, 2

External Slave Peripheral Interface

DMAAck0:3

n/a

n/a

6

0

12

8

PerClk

DMAReq0:3

dc

dc

n/a

n/a

n/a

n/a

PerClk

EOT0:3/TC0:3

dc

dc

8

0

12

8

PerClk

PerAddr0:31

3

1

8

0

19

12

PerClk

PerBLast

3.5

1

6

0

12

8

PerClk

PerCS0

PerCS1:7[GPIO10:16]

n/a

n/a

6

0

12

8

PerClk

PerData0:31

5

1

8

0

19

12

PerClk

PerOE

n/a

n/a

6

0

12

8

PerClk

PerPar0:3

3.5

1

8

0

19

12

PerClk

PerR/W

4

1

6

0

12

8

PerClk

PerReady

6.5

1

n/a

n/a

n/a

n/a

PerClk

PerWBE0:3

3

1

6

0

12

8

PerClk

External Master Peripheral Interface

BusReq

n/a

n/a

6

0

12

8

PerClk

ExtAck

n/a

n/a

6

0

12

8

PerClk

ExtReq

5

1

n/a

n/a

n/a

n/a

PerClk

ExtReset

n/a

n/a

6

0

19

12

PerClk

HoldAck

n/a

n/a

6

0

12

8

PerClk

HoldPri

3

1

n/a

n/a

n/a

n/a

PerClk

HoldReq

5

1

n/a

n/a

n/a

n/a

PerClk

PerClk

n/a

n/a

0.9

0.9

19

12

PLB Clk

4

PerErr

3

1

n/a

n/a

n/a

n/a

PerClk