LRI64 datasheet(30/52 Pages) STMICROELECTRONICS

tên linh kiện	LRI64

Giải thích chi tiết về linh kiện	Memory TAG IC at 13.56 MHz, with 64-bit Unique ID and WORM user area, ISO15693 and ISO18000-3 Mode 1 compliant

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Timing definitions

LRI64

30/52

Timing definitions

Figure 21 shows three specific delay times: t1, t2 and t3. All of them have a minimum value,

specified in Table 14. The t1 parameter also has a maximum and a typical value specified in

Table 14, as summarized in Table 8.

17.1

LRI64 response delay, t1

Upon detection of the rising edge of the EOF received from the VCD, the LRI64 waits for a

time equal to

t1(typ) = 4352 / fC

before starting to transmit its response to a VCD request, or switching to the next slot when

in an inventory process.

17.2

VCD new request delay, t2

t2 is the time after which the VCD may send an EOF to switch to the next slot when one or

more LRI64 responses have been received during an inventory command. It starts from the

reception of the EOF received from the LRI64 devices.

The EOF sent by the VCD is 10% modulated, independent of the modulation index used for

transmitting the VCD request to the LRI64.

t2 is also the time after which the VCD may send a new request to the LRI64 as described in

Figure 18.

t2(min) = 4192 / fC

Table 8.

Timing values(1)

The tolerance of specific timings is ± 32/fC.

Min.

Typ.

Max.

t1(min)

t1(typ) = 4352 / fC

t1(max)

t2(min) = 4192 / fC

——

t1(max) + tSOF

(see notes(2),(3))

tSOF is the duration for the LRI64 to transmit an SOF to the VCD.

t1(max) does not apply for write alike requests. Timing conditions for write alike requests are defined in the

command description.

——

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