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FM25640 bảng dữ liệu(PDF) 8 Page - Ramtron International Corporation |
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FM25640 bảng dữ liệu(HTML) 8 Page - Ramtron International Corporation |
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8 / 13 page ![]() FM25640 - Automotive Temp. Rev. 3.0 July 2007 8 of 13 0 1 2 345 67 0 1 2 34 5 34 5 6 7 0 1 2 345 6 7 op-code 0 0 0 0 0 0 1 0 MSB 13-bit Address X X X 121110 4 3 2 1 0 7 6 5 4 3 2 1 0 LSB MSB LSB CS SCK SI SO Data Figure 9. Memory Write 0 1 2 34567 0 1 2 34 5 3 4 567 0 1 2 34567 op-code 0 0 0 0 0 0 1 MSB 13-bit Address X X X 12 11 10 43 210 76 54321 0 LSB MSB LSB CS SCK SI SO Data 1 Figure 10. Memory Read Endurance Internally, a FRAM operates with a read and restore mechanism similar to a DRAM. Therefore, endurance cycles are applied for each access: read or write. The FRAM architecture is based on an array of rows and columns. Each access causes a cycle for an entire row. Therefore, data locations targeted for substantially differing numbers of cycles should not be located within the same row. In the FM25640, there are 2048 rows each 32 bits wide. Each 4 bytes in the address mark the beginning of a new row. Regardless, FRAM read and write endurance is effectively unlimited at the 4 MHz clock speed. Even at 2000 accesses per second to the same row, 15 years time will pass before 10 12 endurance cycles occur. |
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