SN54HCT573, SN74HCT573

OCTAL TRANSPARENT D-TYPE LATCHES

WITH 3-STATE OUTPUTS

SCLS176E – MARCH 1984 – REVISED JULY 2003

4

POST OFFICE BOX 655303

(unless otherwise noted) (see Figure 1)

PARAMETER

FROM

TO

VCC

TA = 25°C

SN54HCT573

SN74HCT573

UNIT

PARAMETER

(INPUT)

(OUTPUT)

VCC

MIN

TYP

MAX

MIN

MAX

MIN

MAX

UNIT

D

Q

4.5 V

25

35

53

44

t d

D

Q

5.5 V

21

32

48

40

ns

tpd

LE

Any Q

4.5 V

28

35

53

44

ns

LE

Any Q

5.5 V

25

32

48

40

t

OE

Any Q

4.5 V

26

35

53

44

ns

ten

OE

Any Q

5.5 V

23

32

48

40

ns

tdi

OE

Any Q

4.5 V

23

35

53

44

ns

tdis

OE

Any Q

5.5 V

22

32

48

40

ns

tt

Any Q

4.5 V

9

12

18

15

ns

tt

Any Q

5.5 V

9

11

16

14

ns

(unless otherwise noted) (see Figure 1)

PARAMETER

FROM

TO

VCC

TA = 25°C

SN54HCT573

SN74HCT573

UNIT

PARAMETER

(INPUT)

(OUTPUT)

VCC

MIN

TYP

MAX

MIN

MAX

MIN

MAX

UNIT

D

Q

4.5 V

32

52

79

65

t d

D

Q

5.5 V

27

47

71

59

ns

tpd

LE

Any Q

4.5 V

38

52

79

65

ns

LE

Any Q

5.5 V

36

47

71

59

t

OE

Any Q

4.5 V

33

52

79

65

ns

ten

OE

Any Q

5.5 V

28

47

71

59

ns

tt

Any Q

4.5 V

18

42

63

53

ns

tt

Any Q

5.5 V

16

38

57

48

ns

PARAMETER

TEST CONDITIONS

TYP

UNIT

Cpd

Power dissipation capacitance per latch

No load

50

pF

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design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.