ST72324BK2 datasheet(100/188 Pages) STMICROELECTRONICS

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On-chip peripherals

ST72324B

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Table 54.

SPICR register description

Bit

Name

Function

SPIE

Serial Peripheral Interrupt Enable

This bit is set and cleared by software.

0: Interrupt is inhibited.

1: An SPI interrupt is generated whenever SPIF = 1, MODF = 1 or OVR = 1 in the

SPICSR register.

SPE

Serial Peripheral Output Enable

This bit is set and cleared by software. It is also cleared by hardware when, in

master mode, SS = 0 (see Master mode fault (MODF) on page 97). The SPE bit is

cleared by reset, so the SPI peripheral is not initially connected to the external

pins.

0: I/O pins free for general purpose I/O

1: SPI I/O pin alternate functions enabled

SPR2

Divider Enable

This bit is set and cleared by software and is cleared by reset. It is used with the

SPR[1:0] bits to set the baud rate. Refer to Table 55: SPI master mode SCK

frequency.

0: Divider by 2 enabled

1: Divider by 2 disabled

Note: This bit has no effect in slave mode.

4MSTR

Master mode

This bit is set and cleared by software. It is also cleared by hardware when, in

master mode, SS = 0 (see Master mode fault (MODF) on page 97).

0: Slave mode

1: Master mode. The function of the SCK pin changes from an input to an output

and the functions of the MISO and MOSI pins are reversed.

3CPOL

Clock Polarity

This bit is set and cleared by software. This bit determines the idle state of the

serial Clock. The CPOL bit affects both the master and slave modes.

0: SCK pin has a low level idle state

1: SCK pin has a high level idle state

Note: If CPOL is changed at the communication byte boundaries, the SPI must be

disabled by resetting the SPE bit.

2CPHA

Clock Phase

This bit is set and cleared by software.

0: The first clock transition is the first data capture edge.

1: The second clock transition is the first capture edge.

Note: The slave must have the same CPOL and CPHA settings as the master.

1:0 SPR[1:0]

Serial clock frequency

These bits are set and cleared by software. Used with the SPR2 bit, they select

the baud rate of the SPI serial clock SCK output by the SPI in master mode

(seeTable 55).

Note: These 2 bits have no effect in slave mode.

Table 55.

SPI master mode SCK frequency

Serial clock

SPR2

SPR1

SPR0

fCPU/4

fCPU/8

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