TMS470PLF111 datasheet(39/63 Pages) TI

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TMS470PLF111

16/32-BIT RISC FLASH MICROCONTROLLER

SPNS113 – OCTOBER 2006

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251-1443

internal voltage regulator specifications

1 Ramping at minimum tD(VCCIOR)0-3 with large load capacitance Cmin can cause large transient currents (approximately 1.9 A).

Figure 11. PORRST Timing Requirements

VREG recommended operation conditions

VREG halt-mode timing characterisitics(2)(3)

2 These times only reflect VREG transition times. Times for other components are not included.

3 Device low power modes are not supported when the VREG is disabled

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

tD(VCCIOR)0-3

Delay time, 5V input supply to ramp from 0V to 4.75V(1)

tV(PORRST)L

Valid time, PORRST active after 5V input supply becomes

≥ 4.75V

150

VCCIORmin(PORRST)f Minimum input voltage, when PORRST must be made active during power down or brown out

4.75

Cmin(VCC)core

Capacitance distributed over all core VCC pins for voltage regulator stability

ESR(max)core

Total combined ESR of stabilization capacitors on core Vcc pins

00.25

Ω/pin

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

ICC

VCC load rating

Normal mode, regulator active

100

Halt mode, regulator active

PARAMETER

MIN

MAX

UNIT

tnormal-halt

transition time between normal mode and halt mode

thalt-normal

transition time between halt mode and normal mode

μS

VCCP/VCCIOR

PORRST

4.75V

tV(PORRST)L

tD(VCCIOR)0-3

VCCIORmin(PORRST)f

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