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ADL5501AKSZ-R2 bảng dữ liệu(PDF) 16 Page - Analog Devices

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ADL5501AKSZ-R2 bảng dữ liệu(HTML) 16 Page - Analog Devices

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ADL5501
Rev. B | Page 16 of
28
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6
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ADL5501
VPOS
FLTR
RFIN
VRMS
ENBL
COMM
POWER
SUPPLY
RF SIGNAL
GENERATOR
PULSE
GENERATOR
C1
100pF
C2
0.1µF
CFLTR
OSCILLOSCOPE
FET PROBE
ROUT
COUT
AD811
732Ω
50Ω
Figure 34. Hardware Configuration for Output Response to
Enable Gating Measurements
10µs/DIV
400mV rms RF INPUT
250mV rms
160mV rms
70mV rms
ENBL
Figure 35. Output Response to Enable Gating at Various RF Input Levels,
Supply = 3 V, Frequency = 900 MHz, CFLTR = Open, COUT = Open, ROUT = Open
8
0
1
3
5
6
7
0
2000
4000
6000
FREQUENCY (MHz)
2
4
Figure 36. Conversion Gain vs. Frequency, Supply 5 V
40µs/DIV
400mV rms RF INPUT
250mV rms
160mV rms
70mV rms
ENBL
Figure 37. Output Response to Enable Gating at Various RF Input Levels,
Supply = 3 V, Frequency = 900 MHz, CFLTR = 1 nF, COUT = Open, ROUT = Open
100µs/DIV
ENBL
400mV rms RF INPUT
250mV rms
160mV rms
70mV rms
Figure 38. Output Response to Enable Gating at Various RF Input Levels,
Supply = 3 V, Frequency = 900 MHz, CFLTR = Open, COUT = 0.1 μF, ROUT = 1 kΩ
100
0
20
40
60
80
90
10
30
50
70
0
2000
4000
6000
FREQUENCY (MHz)
Figure 39. Intercept vs. Frequency, Supply = 5 V



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