STM32G473MB datasheet(189/229 Pages) STMICROELECTRONICS

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DS12712 Rev 5

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STM32G473xB STM32G473xC STM32G473xE

Electrical characteristics

194

NAND controller waveforms and timings

Figure 49 through Figure 52 represent synchronous waveforms, and Table 101 and

Table 102 provide the corresponding timings. The results shown in these tables are

obtained with the following FMC configuration:

•

COM.FMC_SetupTime = 0x01

•

COM.FMC_WaitSetupTime = 0x03

•

COM.FMC_HoldSetupTime = 0x02

•

COM.FMC_HiZSetupTime = 0x01

•

ATT.FMC_SetupTime = 0x01

•

ATT.FMC_WaitSetupTime = 0x03

•

ATT.FMC_HoldSetupTime = 0x02

•

ATT.FMC_HiZSetupTime = 0x01

•

Bank = FMC_Bank_NAND

•

MemoryDataWidth = FMC_MemoryDataWidth_16b

•

ECC = FMC_ECC_Enable

•

ECCPageSize = FMC_ECCPageSize_512Bytes

•

TCLRSetupTime = 0

•

TARSetupTime = 0

In all timing tables, the THCLK is the HCLK clock period.

Table 100. Synchronous non-multiplexed PSRAM write timings(1)(2)(3)

1. CL = 30 pF.

2. Guaranteed by characterization results.

3. Clock ratio R = (HCLK period /FMC_CLK period).

Symbol

Parameter

Min

Max

Unit

tw(CLK)

FMC_CLK period

R*THCLK - 0.5

td(CLKL-NExL)

FMC_CLK low to FMC_NEx low (x=0..2)

1.5

td(CLKH-NExH)

FMC_CLK high to FMC_NEx high (x= 0…2)

R*THCLK/2 + 1

td(CLKL-NADVL) FMC_CLK low to FMC_NADV low

2.5

td(CLKL-NADVH) FMC_CLK low to FMC_NADV high

3.5

td(CLKL-AV)

FMC_CLK low to FMC_Ax valid (x=16…25)

td(CLKH-AIV)

FMC_CLK high to FMC_Ax invalid (x=16…25)

R*THCLK/2 + 1

td(CLKL-NWEL)

FMC_CLK low to FMC_NWE low

td(CLKH-NWEH)

FMC_CLK high to FMC_NWE high

R*THCLK/2 + 1

td(CLKL-Data)

FMC_D[15:0] valid data after FMC_CLK low

td(CLKL-NBLL)

FMC_CLK low to FMC_NBL low

td(CLKH-NBLH)

FMC_CLK high to FMC_NBL high

R*THCLK/2 + 1.5

tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high

1.5

th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high

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