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STM32G473MB bảng dữ liệu(PDF) 183 Page - STMicroelectronics

tên linh kiện STM32G473MB
Giải thích chi tiết về linh kiện  Arm® Cortex®-M4 32-bit MCUFPU, up to 512 KB Flash, 170 MHz / 213 DMIPS, 128 KB SRAM, rich analog, math accelerator
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
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STM32G473MB bảng dữ liệu(HTML) 183 Page - STMicroelectronics

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DS12712 Rev 5
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STM32G473xB STM32G473xC STM32G473xE
Electrical characteristics
194
Synchronous waveforms and timings
Figure 45 through Figure 48 represent synchronous waveforms and Table 97
through Table 100 provide the corresponding timings. The results shown in these
tables are obtained with the following FMC configuration:
•
BurstAccessMode = FMC_BurstAccessMode_Enable
•
MemoryType = FMC_MemoryType_CRAM
•
WriteBurst = FMC_WriteBurst_Enable
•
CLKDivision = 1
•
DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
In all timing tables, the THCLK is the HCLK clock period.
•
For 2.7 V ≤ VDD ≤ 3.6 V, maximum FMC_CLK = 60 MHz for CLKDIV = 0x1 and 54 MHz
for CLKDIV = 0x0 at CL = 30 pF (on FMC_CLK).
•
For 1.71 V ≤ VDD ≤ 2.7 V, maximum FMC_CLK = 60 MHz for CLKDIV = 0x1 and
32 MHz for CLKDIV = 0x0 at CL= 20 pF (on FMC_CLK).
Figure 45. Synchronous multiplexed NOR/PSRAM read timings
FMC_CLK
FMC_NEx
FMC_NADV
FMC_A[25:16]
FMC_NOE
FMC_AD[15:0]
AD[15:0]
D1
D2
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
tw(CLK)
tw(CLK)
Data latency = 0
BUSTURN = 0
td(CLKL-NExL)
td(CLKH-NExH)
t d(CLKL-NADVL)
td(CLKL-AV)
td(CLKL-NADVH)
td(CLKH-AIV)
td(CLKL-NOEL)
td(CLKH-NOEH)
td(CLKL-ADV)
td(CLKL-ADIV)
tsu(ADV-CLKH)
th(CLKH-ADV)
tsu(ADV-CLKH)
th(CLKH-ADV)
tsu(NWAITV-CLKH)
th(CLKH-NWAITV)
tsu(NWAITV-CLKH)
th(CLKH-NWAITV)
tsu(NWAITV-CLKH)
th(CLKH-NWAITV)
MS32757V1



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