MB95F128MB datasheet(59/80 Pages) FUJITSU

59 / 80 page

MB95120MB Series

(VCC

= 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = −40 °C to + 105 °C)

(Continued)

Parameter

Sym-

bol

name

Condition

Value*2

Unit

Remarks

Min

Max

SCL clock

“L” width

tLOW

SCL0

= 1.7 kΩ,

= 50 pF*1

+ nm / 2) tMCLK − 20

⎯

Master mode

SCL clock

“H” width

tHIGH

SCL0

(nm

/ 2) tMCLK − 20

(nm

/ 2 ) tMCLK + 20

Master mode

Start condition

hold time

tHD;STA

SCL0

SDA0

(

−1 + nm / 2) tMCLK − 20

(

−1 + nm) tMCLK + 20

Master mode

Maximum value is

applied when m,

= 1, 8.

Otherwise, the

minimum value is

applied.

Stop condition

setup time

tSU;STO

SCL0

SDA0

+ nm / 2) tMCLK − 20 (1 + nm / 2) tMCLK + 20

Master mode

Start condition

setup time

tSU;STA

SCL0

SDA0

+ nm / 2) tMCLK − 20 (1 + nm / 2) tMCLK + 20

Master mode

Bus free time

between stop

condition and

start condition

tBUF

SCL0

SDA0

(2 nm

+ 4) tMCLK − 20

⎯

Data hold time tHD;DAT

SCL0

SDA0

3 tMCLK

− 20

⎯

Master mode

Data setup

time

tSU;DAT

SCL0

SDA0

(

−2 + nm / 2) tMCLK − 20 (−1 + nm / 2) tMCLK + 20 ns

Master mode

When assuming

that “L” of SCL is

not extended, the

minimum value is

applied to first bit

of continuous

data.

Otherwise,

the maximum

value is applied.

Setup time

between

clearing

interrupt and

SCL rising

tSU;INT SCL0

(nm

/ 2) tMCLK − 20

(1 + nm

/ 2) tMCLK + 20

Minimum value is

applied to interrupt

at 9th SCL

↓.

Maximum value is

applied to interrupt

at 8th SCL

↓.

SCL clock “L”

width

tLOW

SCL0

4 tMCLK

− 20

⎯

At reception

SCL clock “H”

width

tHIGH

SCL0

4 tMCLK

− 20

⎯

At reception

Start condition

detection

tHD;STA

SCL0

SDA0

2 tMCLK

− 20

⎯

Undetected when

1 tMCLK is used at

reception

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