AL4CE211 datasheet(2/2 Pages) AVERLOGIC

2 / 2 page

AVERLOGIC TECHNOLOGIES, INC.

TEL

: 1 408 361-0400

e-mail: sales@averlogic.com

URL: www.averlogic.com

March 26, 2002

(512, 1k ,2k,

4k, 8k) x9

Memory

Array

Input

Buffer

Output

Buffer

Write

Control

Logic

Read

Control

Logic

Flag Logic

Control Logic

Write Pointer

Read Pointer

Offset

Regissers

Reset Logic

Input data bus

Output data bus

/OE

WCLK

/WEN

/LD

/RS

RCLK

/REN

/FF

/EF

/PAF

/PAE

/RT

Figure 1. AL4CE2x1 FIFO Block Diagram

The 9bit input and output ports operate

independently at a maximum speed of 133

MHz.

The built-in address decoder and

pointer

managing

circuits

provide

straightforward

bus

interface

serially

read/write memory that reduces inter-chip

design efforts. The AL4CE2x1 embedded

memory array and high performance process

technologies

with

extended

controller

functions (read skip, fixed and programmable

status flags.. etc.) offer flexible memory

management.

These FIFOs support 9bit input and output

data bus-width that is controlled by separate

clock and enable signals respectively.

The

input data is acquired at each rising edge of a

free running write clock while a write enable

control pin is asserted.

The output data is

available after each rising edge of a free

running read clock while a read enable and

output enable control pins are asserted. When

output enable (/OE) is LOW, the data output

bus is active. If /OE is HIGH, the output data

bus will be in a high-impedance. This signal

can control whether the data is going to be

skipped during the read operation.

The FIFO Full/Empty and programmable

Almost Full/Almost Empty flags are functions

that

can

help

controlling

software

manipulate the FIFO more easily or to do

retransmit operation.

And the Retransmit

function allows data to be reread from the

FIFO more than once.

These chips are available as a 32pin TQFP

Package

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