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14

Serial Mode

v01.0907

0.5 dB LSB GaAs MMIC 6-BIT DIGITAL

VARIABLE GAIN AMPLIFIER, DC - 6 GHz

The serial mode is enabled then P/S is set to high. Data is entered LSB first and after the 6th shift clock cycle the LE

(Latch Enable) is pulsed High and then Low. See timing diagram below for reference.

Timing Diagram

Direct Parallel Mode - The attenuation state is changed by the Control Voltage Inputs directly. The LE (Latch Enable)

must be at a logic high to control the attenuator in this manner.

Latched Parallel Mode - The attenuation state is selected using the Control Voltage Inputs and set while the LE is in

the Low state. The attenuator will not change state while LE is Low. Once all Control Voltage Inputs are at the desired

states the LE is pulsed. See timing diagram below for reference.

Parameter

Symbol

Vdd = +5V

(Typ.)

Units

Serial Input Setup Time

ts

20

ns

Hold Time from Serial

Input to Shift Clock

th

20

ns

Setup Time from Shift

Clock to Latch Enable

tlsup

40

ns

Propagation Delay

tpd

10

ns

Setup Time for New Data

tsnd

10

ns

Timing