SC16C2550B datasheet(13/43 Pages) PHILIPS

13 / 43 page

SC16C2550B_4

Product data sheet

Rev. 04 — 15 February 2007

13 of 43

NXP Semiconductors

SC16C2550B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

6.6 DMA operation

The SC16C2550B FIFO trigger level provides additional ﬂexibility to the user for block

mode operation. LSR[6:5] provide an indication when the transmitter is empty or has an

empty location(s). The user can optionally operate the transmit and receive FIFOs in the

DMA mode (FCR[3]). When the transmit and receive FIFOs are enabled and the DMA

mode is de-activated (DMA Mode 0), the SC16C2550B activates the interrupt output pin

for each data transmit or receive operation. When DMA mode is activated (DMA Mode 1),

the user takes the advantage of block mode operation by loading or unloading the FIFO in

a block sequence determined by the receive trigger level and the transmit FIFO. In this

mode, the SC16C2550B sets the TXRDY (or RXRDY) output pin when characters in the

transmit FIFO is below 16 or the characters in the receive FIFOs are above the receive

trigger level.

6.7 Loop-back mode

The internal loop-back capability allows on-board diagnostics. In the Loop-back mode, the

normal modem interface pins are disconnected and reconﬁgured for loop-back internally

(see Figure 7). MCR[0:3] register bits are used for controlling loop-back diagnostic testing.

In the Loop-back mode, the transmitter output (TX) and the receiver input (RX) are

disconnected from their associated interface pins and instead are connected together

internally. The CTS, DSR, CD and RI are disconnected from their normal modem control

inputs pins and instead are connected internally to RTS, DTR, MCR[3] (OP2) and MCR[2]

(OP1). Loop-back test data is entered into the transmit holding register via the user data

bus interface, D0 through D7. The transmit UART serializes the data and passes the serial

data to the receive UART via the internal loop-back connection. The receive UART

Table 7.

Baud rate generator programming table using a 1.8432 MHz clock

Output

baud rate

(bit/s)

Output

× clock divisor

(decimal)

Output

× clock divisor

(hexadecimal)

DLM

program value

(hexadecimal)

DLL

program value

(hexadecimal)

2304

900

1536

600

110

1047

417

150

768

300

384

180

600

192

1200

2400

3600

4800

7200

9600

19.2 k

38.4 k

57.6 k

115.2 k

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