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ST72F321AR bảng dữ liệu(PDF) 94 Page - STMicroelectronics

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Giải thích chi tiết về linh kiện  64/44-PIN 8-BIT MCU WITH 32 TO 60K FLASH/ROM, ADC,FIVE TIMERS, SPI, SCI, I2C INTERFACE
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
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SERIAL PERIPHERAL INTERFACE (Cont’d)
10.5.5.4 Single Master Systems
A typical single master system may be configured,
using an MCU as the master and four MCUs as
slaves (see Figure 60).
The master device selects the individual slave de-
vices by using four pins of a parallel port to control
the four SS pins of the slave devices.
The SS pins are pulled high during reset since the
master device ports will be forced to be inputs at
that time, thus disabling the slave devices.
Note: To prevent a bus conflict on the MISO line
the master allows only one active slave device
during a transmission.
For more security, the slave device may respond
to the master with the received data byte. Then the
master will receive the previous byte back from the
slave device if all MISO and MOSI pins are con-
nected and the slave has not written to its SPIDR
register.
Other transmission security methods can use
ports for handshake lines or data bytes with com-
mand fields.
Figure 60. Single Master / Multiple Slave Configuration
MISO
MOSI
MOSI
MOSI
MOSI
MOSI
MISO
MISO
MISO
MISO
SS
SS
SS
SS
SS
SCK
SCK
SCK
SCK
SCK
5V
Slave
MCU
Slave
MCU
Slave
MCU
Slave
MCU
Master
MCU



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