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TMUX1574DYYR bảng dữ liệu(PDF) 28 Page - Texas Instruments |
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TMUX1574DYYR bảng dữ liệu(HTML) 28 Page - Texas Instruments |
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28 / 44 page ![]() SEL S1A S1B D1 S2A S2B VDD EN S4A S4B D4 S3A GND TMUX1574 C D3 Via to GND plane Wide (low inductance) trace for power D2 S3B 28 TMUX1574 SCDS391C – OCTOBER 2018 – REVISED DECEMBER 2019 www.ti.com Product Folder Links: TMUX1574 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Layout Guidelines (continued) Decouple the VDD pin with a 0.1-μF capacitor, placed as close to the pin as possible. Make sure that the capacitor voltage rating is sufficient for the VDD supply. High-speed switches require proper layout and design procedures for optimum performance. Keep the input lines as short as possible. Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup. Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if possible, and only make perpendicular crossings when necessary. 11.2 Layout Example Figure 46. Example Layout |
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