HIGH RIPPLE-REJECTION AND LOW DROPOUT CMOS VOLTAGE REGULATOR

S-1112/1122 Series

Seiko Instruments Inc.

11

Standard Circuit

ON/OFF

VSS

VOUT

VIN

*1

*2

Input

Output

GND

Single GND

*2. A ceramic capacitor of 0.47

Figure 10

Caution The above connection diagram and constant will not guarantee successful operation.

Perform thorough evaluation using the actual application to set the constant.

Application Conditions

1.0

µF or more

0.47

µF or more

ESR of output capacitor:

10

Ω or less

Caution A general series regulator may oscillate, depending on the external components selected.

Check that no oscillation occurs with the application using the above capacitor.