PIC16F72 datasheet(11/14 Pages) MICROCHIP

11 / 14 page

 2002 Microchip Technology Inc.

Preliminary

DS39588A-page 11

PIC16F72

5.0

PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS

5.1

AC/DC Characteristics

TABLE 5-1:

TIMING REQUIREMENTS FOR PROGRAM/VERIFY MODE

Standard Operating Conditions (unless otherwise stated)

Operating Temperature:

+10°C

≤ TA ≤ +40°C

Operating Voltage:

4.5V

≤ VDD ≤ 5.5V

Characteristics

Sym

Min

Typ

Max

Units

Conditions/Comments

General

VDD level for read and verification

VDD

2.0

5.5

VDD level for programming and

erasing

VDDP

4.75

5.25

High voltage on MCLR for chip erase

and program write operations

VPP

12.75

13.25

(Notes 1, 2)

MCLR rise time (VSS to VPP) for Test

mode entry

tVHHR

1.0

µs

(RB6, RB7) input high level

VIH10.8 VDD

Schmitt Trigger input

(RB6, RB7) input low level

VIL10.2 VDD

Schmitt Trigger input

Serial Program/Verify

Data in setup time before clock

↓

tset1

100

Data in hold time after clock

↓

thld1

100

Data input not driven to next clock input

(delay required between

command/data or command/command)

tdly1

1.0

µs

Delay between clock

↓ to clock↑ of next

command or data

tdly2

1.0

µs

Clock

↑ to data out valid (during read

data)

tdly3

200

Erase cycle time

tera

(Note 3)

Programming cycle time

tprog

—

3(4)

Note 1: VPP should be current limited to about 100 mA.

2: VPP must remain above VDDP + 4.0V to remain in Programming mode, while not actually erasing or

programming.

3: The chip erase is self-timed.

4: tprog is expected to be reduced to 1 ms max.

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