LX7220

DS20006704A-page 12

 2022 Microchip Technology Inc. and its subsidiaries

FIGURE 4-4:

Timing Definition for HS-Mode Devices on the I2C Port.

FIGURE 4-5:

Write Cycle Diagram.

FIGURE 4-6:

Read Cycle Diagram.

CONTROL REGISTER BIT DEFINITION

Bit

Name

Value

Description

Status, Address 00h

7:3

Reserved

—

—

2OCP

—

Latched to 1 if the overcurrent limit is reached. Write a “1” to reset the status

flag.

1OTP

—

Latched to 1 if an overtemperature event occurs. Write a “1” to reset the sta-

tus flag.

0

FB_UVLO

—

Latched to 1 if a FB_UVLO event occurs. Write a “1” to reset the status flag.

Vsel, Address 01h, (aka dac)

7EN

1-d

Device enabled.

0

Device disabled.

6:0

VSEL[6:0]

—

7-bit DAC value to set VREF. The default value is determined by the part

ordering code.

Ctrl1, Address 02h, (aka reg2)

7:6

Reserved

00-d

—