TUSB564 datasheet(6/52 Pages) TI

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5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature and voltage range (unless otherwise noted)(1)

MIN

MAX

UNIT

VCC

Supply voltage range

–0.3

VIN_DIFF

Differential voltage at differential inputs

±2.5

VIN_SE

Input voltage at differential Inputs

–0.5

VIN_CMOS

Input voltage at CMOS inputs

–0.3

Junction temperature

125

°C

TSTG

Storage temperature

–65

150

°C

(1)

Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.

If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

5.2 ESD Ratings

VALUE

UNIT

V(ESD)

Electrostatic discharge

Human body model (HBM), per AEC

Q100-002(1), all pins

±4000

Charged device model (CDM), per AEC

Q100-011, all pins

±1500

(1)

AEC Q100-002 indicates that HBM stressing must be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

5.3 Recommended Operating Conditions

over operating free-air temperature and voltage range (unless otherwise noted)

MIN

NOM

MAX

UNIT

VCC

Supply voltage

3.3

3.6

VCC_RAMP

Power supply ramp

0.1

100

VI2C

Supply that external resistors on SDA and SCL are pulled up too

1.7

3.6

VPSN

Power supply noise on VCC

100

Ambient temperature

–40

105

°C

TPCB

PCB temperature (1mm away from the device)

–40

112

°C

5.4 Thermal Information

THERMAL METRIC(1)

Device

UNIT

RGF (VQFN)

40 PINS

RθJA

Junction-to-ambient thermal resistance

29.3

°C/W

RθJC(top)

Junction-to-case (top) thermal resistance

18.6

°C/W

RθJB

Junction-to-board thermal resistance

10.8

°C/W

ΨJT

Junction-to-top characterization parameter

0.3

°C/W

ΨJB

Junction-to-board characterization parameter

10.7

°C/W

RθJC(bot)

Junction-to-case (bottom) thermal resistance

3.5

°C/W

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

note.

TUSB564-Q1

SLLSFO9A – MAY 2024 – REVISED SEPTEMBER 2024

www.ti.com

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