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MCP16501 bảng dữ liệu(PDF) 14 Page - Microchip Technology

tên linh kiện MCP16501
Giải thích chi tiết về linh kiện  Cost and Size Optimized PMIC for SAMA5DX/SAM9X6/SAM9X7/SAMA7G Series MPUs
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MCP16501
DS20006388E-page 14
 2020-2022 Microchip Technology Inc. and its subsidiaries
3.0
PIN DESCRIPTION
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
Pin Number
Pin Name
Description
1
OUT1
Output Sensing for Buck Channel 1. Connect to the regulation point for VOUT1.
2
nRSTO
Active-Low, Open-Drain Reset Output.
3
PWRHLD
Power Hold Input. Typically asserted as high by the MPU to maintain power after
the initial start-up is triggered by nSTRT. PWRHLD is to be asserted as low by the
MPU to initiate a PMIC shutdown sequence.
4LPM
Low-Power Mode Input pin. In combination with PWRHLD, this pin defines the
power mode status of the MCP16501.
5nSTRTO
Active-Low, Open-Drain Start Event Output. nSTRTO is asserted low whenever
nSTRT is low.
6
OUT2
Output Sensing for Buck Channel 2. Connect to the regulation point for VOUT2.
7
PVIN2
Power Input Voltage of Buck Channel 2. Connect a ceramic capacitor from PVIN2
to the PGND2 pin to localize pulsed current loops and decouple switching noise.
8SW2
Switch Node of Buck Channel 2. Internal power MOSFET switches and external
inductor connection.
9
PGND2
Power Ground of Buck Channel 2.
10
PGND3
Power Ground of Buck Channel 3.
11
SW3
Switch Node of Buck Channel 3. Internal power MOSFET switches and external
inductor connection.
12
PVIN3
Power Input Voltage of Buck Channel 3. Connect a ceramic capacitor from PVIN3
to the PGND3 pin to localize pulsed current loops and decouple switching noise.
13
OUT3
Output Sensing for Buck Channel 3. Connect to the regulation point for VOUT3.
14
nSTRT
Start Event Input. Drive nSTRT to low to initiate a start-up sequence. nSTRT is
pulled up internally. A capacitor can be connected to nSTRT to automatically initiate
a power-up sequence when the main supply rises.
15
SELV3
Buck Channel 3 Output Voltage Selection pin. Three-state input.
16
SGND
Signal Ground. Connect to reference ground plane.
17
VIN
Input voltage for the LDO and for the analog control circuitry. Decouple VIN to
SGND with a 2.2uF (minimum) ceramic capacitor.
18
LOUT
LDO Output. Decouple LOUT to ground with a 2.2 µF (minimum) ceramic capacitor.
19
LFB
LDO FB pin. Connect to an external resistor divider to LOUT for output voltage
adjustment.
20
SELV2
Buck Channel 2 Output Voltage Selection pin. Three-state input.
21
LEN
LDO Enable input.
22
PGND1
Power Ground of Buck Channel 1.
23
SW1
Switch Node of Buck Channel 1. Internal power MOSFET switches and external
inductor connection.
24
PVIN1
Power Input Voltage of Buck Channel 1. Connect a ceramic capacitor from PVIN1
to the PGND1 pin to localize pulsed current loops and decouple switching noise.
—
EP
Exposed Pad. Connect to ground plane with vias to ensure good thermal
properties.



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