CYRF69103
Document #: 001-07611 Rev *B
Page 29 of 73
Low-Voltage Detect Control
POR Compare State
Table 39.Low-voltage Control Register (LVDCR) [0x1E3] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Reserved
PORLEV[1:0]
Reserved
VM[2:0]
Read/Write
–
–
R/W
R/W
–
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
This register controls the configuration of the Power-on Reset/Low-voltage Detection circuit. This register can only be accessed in the second
bank of I/O space. This requires setting the XIO bit in the CPU flags register.
Bits 7:6
Reserved
Bits 5:4
PORLEV[1:0]
This field controls the level below which the precision power-on-reset (PPOR) detector generates a reset
0 0 = 2.7V Range (trip near 2.6V)
0 1 = 3V Range (trip near 2.9V)
1 0 = Reserved
1 1 = PPOR will not generate a reset, but values read from the Voltage Monitor Comparators Register (
Table 40) give the inter-
nal PPOR comparator state with trip point set to the 3V range setting.
Bit 3
Reserved
Bits 2:0
VM[2:0]
This field controls the level below which the low-voltage-detect trips—possibly generating an interrupt and the level at which the
Flash is enabled for operation.
VM[2:0]
LVD Trip Point (V)
Min.
Max.
Typical
000
2.69
2.72
2.7
001
2.90
2.94
2.92
010
3.00
3.04
3.02
011
3.10
3.15
3.13
100
Reserved
101
Reserved
110
Reserved
111
Reserved
Table 40.Voltage Monitor Comparators Register (VLTCMP) [0x1E4] [R]
Bit #
7
6
5
4
3
2
1
0
Field
Reserved
LVD
PPOR
Read/Write
–
–
–
–
–
–
R
R
Default
0
0
0
0
0
0
0
0
This read-only register allows reading the current state of the Low-voltage Detection and Precision-Power-On-Reset comparators
Bits 7:2
Reserved
Bit 1
LVD
This bit is set to indicate that the low-voltage-detect comparator has tripped, indicating that the supply voltage has gone below
the trip point set by VM[2:0] (See
Table 39.)
0 = No low-voltage-detect event
1 = A low-voltage-detect has tripped
Bit 0
PPOR
This bit is set to indicate that the precision-power-on-reset comparator has tripped, indicating that the supply voltage is below
the trip point set by PORLEV[1:0]
0 = No precision-power-on-reset event
1 = A precision-power-on-reset event has tripped
Note This register can only be accessed in the second bank of I/O space. This requires setting the XIO bit in the CPU flags register
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