PCAL6408APW datasheet(13/59 Pages) NXP

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NXP Semiconductors

PCAL6408A

Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander with interrupt output, reset, and

configuration registers

cleared, assuming there were no additional input(s) that have changed, and bit 4 of the input port register reads

‘1’. The next read of the input port register bit 4 should now read ‘0’.

An interrupt remains active when a non-latched input simultaneously switches state with a latched input and

then returns to its original state. A read of the input port register reflects only the change of state of the latched

input and also clears the interrupt. The interrupt is not cleared if the input latch register changes from latched to

non-latched configuration.

If the input pin is changed from latched to non-latched input, a read from the input port register reflects the

current port logic level. If the input pin is changed from non-latched to latched input, the read from the input port

Bit

Symbol

Default

Table 13. Input latch register (address 42h)

7.4.7 Pull-up/pull-down enable register (43h)

This register allows the user to enable or disable pull-up/pull-down resistors on the I/O pins. Setting the bit to

logic 1 enables the selection of pull-up/pull-down resistors. Setting the bit to logic 0 disconnects the pull-up/pull-

down resistors from the I/O pins. Also, the resistors are disconnected when the outputs are configured as open-

drain outputs (see Section 7.4.11). Use the pull-up/pull-down selection registers to select either a pull-up or pull-

down resistor.

Bit

Symbol

PE7

PE6

PE5

PE4

PE3

PE2

PE1

PE0

Default

Table 14. Pull-up/pull-down enable register (address 43h)

7.4.8 Pull-up/pull-down selection register (44h)

The I/O port can be configured to have pull-up or pull-down resistor by programming the pull-up/pull-down

selection register. Setting a bit to logic 1 selects a 100 kΩ pull-up resistor for that I/O pin. Setting a bit to logic

0 selects a 100 kΩ pull-down resistor for that I/O pin. If the pull-up/down feature is disconnected, writing to this

Bit

Symbol

PUD7

PUD6

PUD5

PUD4

PUD3

PUD2

PUD1

PUD0

Default

Table 15. Pull-up/pull-down selection register (address 44h)

7.4.9 Interrupt mask register (45h)

Interrupt mask register is set to logic 1 upon power-on, disabling interrupts during system start-up. Interrupts

may be enabled by setting corresponding mask bits to logic 0. If an input changes state and the corresponding

bit in the Interrupt mask register is set to 1, the interrupt is masked and the interrupt pin (INT) is not asserted. If

the corresponding bit in the Interrupt mask register is set to 0, the interrupt pin is asserted.

When an input changes state and the resulting interrupt is masked (interrupt mask bit is 1), setting the input

mask register bit to 0 causes the interrupt pin to be asserted. If the interrupt mask bit of an input that is currently

the source of an interrupt is set to 1, the interrupt pin is de-asserted.

PCAL6408A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3.3 — 14 October 2024

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