PM7367 datasheet(315/323 Pages) PMC

315 / 323 page

PM7367 FREEDM-32P32

DATA SHEET

PMC-1991499

ISSUE 2

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE

301

FREEDM-32P32 TIMING CHARACTERISTICS

(TA = -40°C to +85°C, VDD = 3.3 V ±10%, VBIAS = 5.0V ±10%)

Table 32 – FREEDM-32P32 Link Input (Figure 38, Figure 39)

Symbol

Description

Min

Max

Units

RCLK[31:0] Frequency (See Note 3) 1.542

1.546

MHz

RCLK[31:0] Frequency (See Note 4) 2.046

2.05

MHz

RCLK[2:0] Frequency (See Note 5)

MHz

RCLK[31:3] Frequency (See Note 5)

MHz

RCLK[31:0] Duty Cycle

SYSCLK Frequency

MHz

SYSCLK Duty Cycle

tSRD

RD[31:3] Set-Up Time

tHRD

RD[31:3] Hold Time

tSRD

RD[2:0] Set-Up Time

tHRD

RD[2:0] Hold Time

tSTBD

TBD Set-Up Time (See Note 6)

tHTBD

TBD Hold Time

Notes on Input Timing:

1. When a set-up time is specified between an input and a clock, the set-up

time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4

Volt point of the clock.

2. When a hold time is specified between an input and a clock, the hold time is

the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt

point of the input.

3. Applicable only to channelised T1 links and measured between framing bits.

4. Applicable only to channelised E1 links and measured between framing

bytes.

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