PM7367 datasheet(226/323 Pages) PMC

226 / 323 page

PM7367 FREEDM-32P32

DATA SHEET

PMC-1991499

ISSUE 2

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE

212

XFER[2:0]:

The indirect channel transfer size (XFER[2:0]) specifies the amount of data

the partial packet processor requests from the TMAC block. The channel

transfer size to be written to the channel provision RAM, in an indirect write

operation, must be set up in this register before triggering the write. When

the channel FIFO free space reaches or exceeds the limit specified by

XFER[2:0], the partial packet processor will make a request for data to the

TMAC to retrieve the XFER[2:0] + 1 blocks of data. FIFO free space and

transfer size are measured in the number of 16-byte blocks. XFER[2:0]

reflects the value written until the completion of a subsequent indirect channel

read operation.

To prevent lockup, the channel transfer size (XFER[2:0]) can be configured to

be less than or equal to the start transmission level set by LEVEL[3:0] and

TRANS. Alternatively, the channel transfer size can be set, such that, the

total number of blocks in the logical channel FIFO minus the start

transmission level is an integer multiple of the channel transfer size.

The case of a single block transfer size is a special. When BURSTEN is set

high and XFER[2:0] = 'b000, the transfer size is variable. The THDL will

request the TMAC to transfer as much data as there is free space in the

FIFO, up to a maximum set by BURST[2:0].

FLAG[2:0]:

The flag insertion control (FLAG[2:0]) configures the minimum number of

flags or bytes of idle bits the HDLC processor inserts between HDLC packets.

The value of FLAG[2:0] to be written to the channel provision RAM, in an

indirect channel write operation, must be set up in this register before

triggering the write. The minimum number of flags or bytes of idle (8 bits of

1's) inserted between HDLC packets is shown in the table below. FLAG[2:0]

reflects the value written until the completion of a subsequent indirect channel

read operation.

Table 23 – FLAG[2:0] Settings

FLAG[2:0]

Minimum Number of Flag/Idle Bytes

000

1 flag / 0 Idle byte

001

2 flags / 0 idle byte

010

4 flags / 2 idle bytes

011

8 flags / 6 idle bytes

100

16 flags / 14 idle bytes

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