PM7366-PI datasheet(168/286 Pages) PMC

tên linh kiện	PM7366-PI

Giải thích chi tiết về linh kiện	FRAME ENGINE AND DATA LINK MANAGER

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Trang chủ	http://www.pmc-sierra.com

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RELEASED

PM7366 FREEDM-8

DATA SHEET

PMC-1970930

ISSUE 4

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

155

CACHE:

The transmit descriptor reference cache enable bit (CACHE) controls the frequency at which

TDRs are written to the TDR Free Queue. When CACHE is set high, freed TDRs are cache

and then written up to six at a time. When CACHE is set low, freed TDRs are written one at a

time.

TDQ_RDYN[2:0]:

The TDQ_RDYN[2:0] field sets the number of transmit descriptor references (TDRs) that

must be read from the TDR Ready Queue before the TDR Ready interrupt (TDQRDYI) is

asserted, as follows:

Table 22 – TDQ_RDYN[2:0] Settings

TDQ_RDYN[2:0]

No of TDRs

000

001

010

011

100

101

110

Reserved

111

Reserved

TDQ_FRN[1:0]:

The TDQ_FRN[1:0] field sets the number of times that a block of TDRs are written to the TDR

Free Queue from the TMACs internal cache before the TDR Free Queue Interrupt (TDQFI) is

asserted, as follows:

Table 23 – TDQ_FRN[1:0] Settings

TDQ_FRN[1:0]

No of Reads

Reserved

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