PM7366-PI datasheet(115/286 Pages) PMC

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RELEASED

PM7366 FREEDM-8

DATA SHEET

PMC-1970930

ISSUE 4

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

102

LINK[2:0]:

The indirect link number bits (LINK[2:0]) select amongst the 8 receive links to be configured or

interrogated in the indirect access.

RWB:

The indirect access control bit (RWB) selects between a configure (write) or interrogate (read)

access to the channel provision RAM. The address to the channel provision RAM is

constructed by concatenating the TSLOT[4:0] and LINK[2:0] bits. Writing a logic zero to RWB

triggers an indirect write operation. Data to be written is taken from the PROV, the CDLBEN

and the CHAN[6:0] bits of the RCAS Indirect Channel Data register. Writing a logic one to

RWB triggers an indirect read operation. Addressing of the RAM is the same as in an indirect

write operation. The data read can be found in the PROV, the CDLBEN and the CHAN[6:0]

bits of the RCAS Indirect Channel Data register.

BUSY:

The indirect access status bit (BUSY) reports the progress of an indirect access. BUSY is set

high when this register is written to trigger an indirect access, and will stay high until the

access is complete. At which point, BUSY will be set low. This register should be polled to

determine when data from an indirect read operation is available in the RCAS Indirect

Channel Data register or to determine when a new indirect write operation may commence.

Reserved[1:0]:

The reserved bits (Reserved[1:0]) must be set low for the correct operation of the FREEDM-8

device.

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