PM7366-PI datasheet(276/286 Pages) PMC

276 / 286 page

RELEASED

PM7366 FREEDM-8

DATA SHEET

PMC-1970930

ISSUE 4

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

263

FREEDM-8 TIMING CHARACTERISTICS

(TA = -40°C to +85°C, VDD = 3.3 V ±10%, VBIAS = 5.0V ±10%)

Table 34 – FREEDM-8 Link Input (Figure 38, Figure 39)

Symbol

Description

Min

Max

Units

RCLK[7:0] Frequency (See Note 3)

1.542

1.546

MHz

RCLK[7:0] Frequency (See Note 4)

2.046

2.05

MHz

RCLK[2:0] Frequency (See Note 5)

MHz

RCLK[7:3] Frequency (See Note 5)

MHz

RCLK[7:0] Duty Cycle

SYSCLK Frequency

MHz

SYSCLK Duty Cycle

tSRD

RD[7:3] Set-Up Time

tHRD

RD[7:3] Hold Time

tSRD

RD[2:0] Set-Up Time

tHRD

RD[2:0] Hold Time

tSTBD

TBD Set-Up Time (See Note 6)

tHTBD

TBD Hold Time

Notes on Input Timing:

1. When a set-up time is specified between an input and a clock, the set-up time is the time in

nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.

2. When a hold time is specified between an input and a clock, the hold time is the time in

nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input.

3. Applicable only to channelised T1 links and measured between framing bits.

4. Applicable only to channelised E1 links and measured between framing bytes.

5. Applicable only to unchannelised links of any format and measured between any two RCLK

rising edges.

6. TBD set-up time is measured with a 20 pF load on TBCLK. The set-up time increases by 1 ns

for each 10 pF of extra load on TBCLK.

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