PM7366-PI datasheet(190/286 Pages) PMC

190 / 286 page

RELEASED

PM7366 FREEDM-8

DATA SHEET

PMC-1970930

ISSUE 4

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

177

Bit

Type

Function

Default

Bit 31 to

Bit 16

Unused

XXXXH

Bit 15

R/W

7BIT

Bit 14

R/W

PRIORITYB

Bit 13

R/W

INVERT

Bit 12

R/W

DFCS

Bit 11

Unused

Bit 10

Unused

Bit 9

Unused

Bit 8

FLEN[8]

Bit 7

FLEN[7]

Bit 6

FLEN[6]

Bit 5

FLEN[5]

Bit 4

FLEN[4]

Bit 3

FLEN[3]

Bit 2

FLEN[2]

Bit 1

FLEN[1]

Bit 0

FLEN[0]

This register contains data to be inserted into the channel provision RAM in an indirect write

operation.

Note

This register is not byte addressable. Writing to this register modifies all the bits in the register.

Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all

four byte enables are negated, no access is made to this register.

FLEN[8:0]:

The indirect FIFO length (FLEN[8:0]) is the number of blocks, less one, that is provisioned to

the circular channel FIFO specified by the FPTR[8:0] block pointer. The FIFO length to be

written to the channel provision RAM, in an indirect channel write operation, must be set up in

this register before triggering the write.

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