PM7364 datasheet(39/325 Pages) PMC

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RELEASED

PM7364 FREEDM-32

DATA SHEET

PMC-1960758

ISSUE 6

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE

Pin Name

Type

No.

Function

TDO

Tristate

Output

K18

The test data output signal (TDO) carries test

data out of the FREEDM-32 via the IEEE P1149.1

test access port. TDO is updated on the falling

edge of TCK. TDO is a tri-state output which is

inactive except when scanning of data is in

progress.

TRSTB

Input

J17

The active low test reset signal (TRSTB) provides

an asynchronous FREEDM-32 test access port

reset via the IEEE P1149.1 test access port.

TRSTB is an asynchronous input with an integral

pull up resistor.

Note that when TRSTB is not being used, it must

be connected to the RSTB input.

VBIAS[3:1] Input

H20

The bias signals (VBIAS[3:1]) provide 5 Volt bias

to input and I/O pads to allow the FREEDM-32 to

tolerate connections to 5 Volt devices. To avoid

damage to the device, the VBIAS[3:1] signals

must be connected together externally and must

at all times be kept at a voltage that is equal to or

higher than the VDD[28:1] power supplies. In a

3.3V operating environment, VBIAS[3:1] and

VDD[28:1] may be connected together. In a 5V

operating environment, VBIAS[3:1] should be

powered up to 5V before VDD[28:1] are powered

up to 3.3V.

EN5V

Input

D17

The 5 Volt PCI signalling enable signal (EN5V)

causes the PCI Host Interface Signals to operate

in the 5V PCI signalling environment when set

high and the 3.3V PCI signalling environment

when set low. EN5V is an asynchronous input

with an integral pull up resistor.

Open

U17

This pin must be left unconnected.

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