ST10F269ZX datasheet(146/184 Pages) STMICROELECTRONICS

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ST10F269

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A complete conversion will take 14

tCC + 2 tSC + 4 TCL (fastest convertion rate = 6.06µs at 32MHz). This

time includes the conversion itself, the sample time and the time required to transfer the digital value to

the result register.

21.4 - AC characteristics

21.4.1 - Test Waveforms

21.4.2 - Definition of Internal Timing

The internal operation of the ST10F269 is

controlled by the internal CPU clock fCPU. Both

edges of the CPU clock can trigger internal (for

example pipeline) or external (for example bus

cycles) operations.

The specification of the external timing (AC

Characteristics) therefore depends on the time

Table 43 : ADC Sampling and Conversion Timing (TQFP144 devices)

ADCON.15/14

ADCTC

Conversion Clock tCC

ADCON.13/12

ADSTC

Sample Clock tSC

TCL = 1/2 x fXTAL

At fCPU = 32MHz

tSC =

At fCPU = 32MHz

and ADCTC = 00

TCL x 24

0.375

µs00

tCC

0.375

µs

Reserved, do not use

Reserved

tCC x 2

0.75

µs

TCL x 96

1.5

µs10

tCC x 4

1.50

µs

TCL x 48

0.75

µs11

tCC x 8

3.00

µs

Figure 66 : Input / Output Waveforms

Figure 67 : Float Waveforms

2.4V

0.45V

Test Points

0.2VDD+0.9

0.2VDD-0.1

AC inputs during testing are driven at 2.4V for a logic ‘1’ and 0.4V for a logic ‘0’.

Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’.

Timing

Reference

Points

VLoad +0.1V

VLoad -0.1V

VOH -0.1V

VOL +0.1V

VLoad

VOL

VOH

For timing purposes a port pin is no longer floating when VLOAD changes of ±100mV.

It begins to float when a 100mV change from the loaded VOH/VOL level occurs (IOH/IOL = 20mA).

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