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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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ST10F269ZX bảng dữ liệu(PDF) 82 Page - STMicroelectronics |
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ST10F269ZX bảng dữ liệu(HTML) 82 Page - STMicroelectronics |
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82 / 184 page  12 - PARALLEL PORTS ST10F269 82/184 Port 5 pins have a special port structure (see Figure 35), first because it is an input only port, and second because the analog input channels are directly connected to the pins rather than to the input latches. 12.8.2 - Port 5 Schmitt Trigger Analog Inputs A Schmitt trigger protection can be activated on each pin of Port 5 by setting the dedicated bit of register P5DIDIS. P5DIDIS (FFA4h / D2h) SFR Reset Value: 0000h 12.9 - Port 6 If this 8-bit port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction register DP6. Each port line can be switched into push/pull or open drain mode via the open drain control register ODP6. P6 (FFCCh / E6h) SFR Reset Value: --00h DP6 (FFCEH / E7H) SFR Reset Value: --00h Figure 35 : Block Diagram of a Port 5 Pin 15 14 13 12 11 10 98 765 432 10 P5DI DIS.15 P5DI DIS.14 P5DI DIS.13 P5DI DIS.12 P5DI DIS.11 P5DI DIS.10 P5DI DIS.9 P5DI DIS.8 P5DI DIS.7 P5DI DIS.6 P5DI DIS.5 P5DI DIS.4 P5DI DIS.3 P5DI DIS.2 P5DI DIS.1 P5DI DIS.0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW P5DIDIS.y Port 5 Digital Disable Register Bit y P5DIDIS.y = 0: Port line P5.y digital input is enabled (Schmitt trigger enabled) P5DIDIS.y = 1: Port line P5.y digital input is disabled (Schmitt trigger disabled, necessary for input leakage current reduction) 15 14 13 12 11 10 98 765 432 10 - - - - - - - - P6.7 P6.6 P6.5 P6.4 P6.3 P6.2 P6.1 P6.0 RW RW RW RW RW RW RW RW P6.y Port Data Register P6 Bit y 15 14 13 12 11 10 98 765 432 10 --- -- --- DP6.7 DP6.6 DP6.5 DP6.4 DP6.3 DP6.2 DP6.1 DP6.0 RW RW RW RW RW RW RW RW Read Port P5.y Input Latch Clock P5.y/ANy Read Buffer to Sample + Hold Circuit Channel Select Analog Switch y = 15...0 |
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