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SN74HCS166DYYR bảng dữ liệu(PDF) 8 Page - Texas Instruments |
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SN74HCS166DYYR bảng dữ liệu(HTML) 8 Page - Texas Instruments |
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8 / 35 page ![]() 6 Parameter Measurement Information tpd is the maximum between tPLH and tPHL Figure 6-1. Load Circuit Figure 6-2. Voltage Waveforms Pulse Durations Figure 6-3. Voltage Waveforms Setup and Hold and Input Rise and Fall Times Figure 6-4. Voltage Waveforms Propagation Delay and Output Transition Times A. CL includes probe and jig capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following charactersitics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50% D. The outputs are measured one at a time with one input transition per measurement. SN54HC166, SN74HC166 SCLS117E – DECEMBER 1982 – REVISED FEBRUARY 2022 www.ti.com 8 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HC166 SN74HC166 |
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